The Experts below are selected from a list of 4977 Experts worldwide ranked by ideXlab platform
Raphael Weber - One of the best experts on this subject based on the ideXlab platform.
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IESS - Low–Level Space Optimization of an AES Implementation for a Bit–Serial Fully Pipelined Architecture
IFIP Advances in Information and Communication Technology, 2009Co-Authors: Raphael Weber, Achim RettbergAbstract:A previously developed AES (Advanced Encryption Standard) implementation is optimized and described in this paper. The special architecture for which this implementation is targeted comprises synchronous and Systematic Bit–serial processing without a central controlling instance. In order to shrink the design in terms of logic utilization we deeply analyzed the architecture and the AES implementation to identify the most costly logic elements. We propose to merge certain parts of the logic to achieve better area efficiency. The approach was integrated into an existing synthesis tool which we used to produce synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran tests on an FPGA board.
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ARC - Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
Lecture Notes in Computer Science, 2009Co-Authors: Raphael Weber, Achim RettbergAbstract:This paper describes the implementation of the Advanced Encryption Standard (AES) for a specific hardware architecture, which was developed based on the combination of different design paradigms. The architecture comprises synchronous and Systematic Bit---serial processing without a central controlling instance. To realize the AES cipher, we extended the architecture by designing specific elements. That means, we deeply analyzed the encryption algorithm and identified hardware characteristics leading to an optimal area and run---time efficient implementation. The implementation of AES is done with the developed synthesis tool of the hardware architecture in synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran some tests on an FPGA board.
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SBCCI - Optimization techniques for a reconfigurable, self-timed, and Bit-serial architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07, 2007Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper presents latency optimizations for a specific hard-ware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and Systematic Bit-serial processing with-out a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.
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ReConFig - Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture
2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), 2006Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous Bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and Systematic Bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture.
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EUC - Path concepts for a reconfigurable Bit-serial synchronous architecture
Embedded and Ubiquitous Computing – EUC 2005, 2005Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous Bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and Systematic Bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture. The example – implementing both algorithms in one operator network – broadens the application area of the architecture significantly.
Achim Rettberg - One of the best experts on this subject based on the ideXlab platform.
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IESS - Low–Level Space Optimization of an AES Implementation for a Bit–Serial Fully Pipelined Architecture
IFIP Advances in Information and Communication Technology, 2009Co-Authors: Raphael Weber, Achim RettbergAbstract:A previously developed AES (Advanced Encryption Standard) implementation is optimized and described in this paper. The special architecture for which this implementation is targeted comprises synchronous and Systematic Bit–serial processing without a central controlling instance. In order to shrink the design in terms of logic utilization we deeply analyzed the architecture and the AES implementation to identify the most costly logic elements. We propose to merge certain parts of the logic to achieve better area efficiency. The approach was integrated into an existing synthesis tool which we used to produce synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran tests on an FPGA board.
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ARC - Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
Lecture Notes in Computer Science, 2009Co-Authors: Raphael Weber, Achim RettbergAbstract:This paper describes the implementation of the Advanced Encryption Standard (AES) for a specific hardware architecture, which was developed based on the combination of different design paradigms. The architecture comprises synchronous and Systematic Bit---serial processing without a central controlling instance. To realize the AES cipher, we extended the architecture by designing specific elements. That means, we deeply analyzed the encryption algorithm and identified hardware characteristics leading to an optimal area and run---time efficient implementation. The implementation of AES is done with the developed synthesis tool of the hardware architecture in synthesizable VHDL code. For testing purposes, we simulated the generated VHDL code and ran some tests on an FPGA board.
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SBCCI - Optimization techniques for a reconfigurable, self-timed, and Bit-serial architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07, 2007Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper presents latency optimizations for a specific hard-ware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and Systematic Bit-serial processing with-out a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.
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ReConFig - Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture
2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), 2006Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous Bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and Systematic Bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture.
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EUC - Path concepts for a reconfigurable Bit-serial synchronous architecture
Embedded and Ubiquitous Computing – EUC 2005, 2005Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous Bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and Systematic Bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture. The example – implementing both algorithms in one operator network – broadens the application area of the architecture significantly.
Yunghsiang S. Han - One of the best experts on this subject based on the ideXlab platform.
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A Systematic Bit-wise decomposition of M-ary symbol metric
IEEE Transactions on Wireless Communications, 2006Co-Authors: Chia-wei Chang, Po-ning Chen, Yunghsiang S. HanAbstract:In this paper, we present a Systematic recursive formula for Bit-wise decomposition of M-ary symbol metric. The decomposed Bit metrics can be applied to improve the performance of a system where the information sequence is binary-coded and interleaved before M-ary modulated. A traditional receiver designed for certain system is to de-map the received M-ary symbol into its binary isomorphism so as to facilitate the subsequent Bit-based manipulation, such as hard-decision decoding. With a Bit-wise decomposition of M-ary symbol metric, a soft-decision decoder can be used to achieve a better system performance. The idea behind the Systematic formula is to decompose the symbol-based maximum-likelihood (ML) metric by equating a number of specific equations that are drawn from squared-error criterion. It interestingly yields a Systematic recursive formula that can be applied to some previous work derived from different standpoint. Simulation results based on IEEE 802.11a/g standard show that at Bit-error-rate of 10-5 , the proposed Bit-wise decomposed metric can provide 3.0 dB, 3.9 dB and 5.1 dB improvement over the concatenation of binary-demapper, deinterleaver and hard-decision decoder respectively for 16QAM, 64QAM and 256QAM symbols, in which the in-phase and quadrature components in a complex M2-QAM symbol are independently treated as two real M-PAM symbols. Further empirical study on system imperfection implies that the proposed Bit-wise decomposed metric also improves the system robustness against gain mismatch and phase imperfection. In the end, a realization structure that avails the recursive nature of the proposed Bit-decomposed metric formula is addressed
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Realization of a Systematic Bit-wise decomposition metric
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems 2004. Proceedings., 1Co-Authors: Chia-wei Chang, Po-ning Chen, Yunghsiang S. HanAbstract:A realization structure for our previously proposed Systematic recursive formula for Bit-wise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.
Florian Dittmann - One of the best experts on this subject based on the ideXlab platform.
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SBCCI - Optimization techniques for a reconfigurable, self-timed, and Bit-serial architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07, 2007Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper presents latency optimizations for a specific hard-ware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and Systematic Bit-serial processing with-out a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.
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ReConFig - Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture
2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), 2006Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous Bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and Systematic Bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture.
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EUC - Path concepts for a reconfigurable Bit-serial synchronous architecture
Embedded and Ubiquitous Computing – EUC 2005, 2005Co-Authors: Florian Dittmann, Achim Rettberg, Raphael WeberAbstract:This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous Bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and Systematic Bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture. The example – implementing both algorithms in one operator network – broadens the application area of the architecture significantly.
H.r. Telle - One of the best experts on this subject based on the ideXlab platform.
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Word-Synchronous Optical Sampling of Periodically Repeated OTDM Data Words for True Waveform Visualization
Journal of Lightwave Technology, 2007Co-Authors: E. Benkler, H.r. TelleAbstract:An improved phase-locked loop (PLL) for versatile synchronization of a sampling pulse train to an optical data stream is presented. It enables optical sampling of the true waveform of repetitive high Bit-rate optical time division multiplexed (OTDM) data words such as pseudorandom Bit sequences. Visualization of the true waveform can reveal details, which cause Systematic Bit errors. Such errors cannot be inferred from eye diagrams and require word-synchronous sampling. The programmable direct-digital-synthesis circuit used in our novel PLL approach allows flexible adaption of virtually any problem-specific synchronization scenario, including those required for waveform sampling, for jitter measurements by slope detection, and for classical eye-diagrams. Phase comparison of the PLL is performed at 10-GHz OTDM base clock rate, leading to a residual synchronization jitter of less than 70 fs.
