The Experts below are selected from a list of 141 Experts worldwide ranked by ideXlab platform
Jan-ou Wu - One of the best experts on this subject based on the ideXlab platform.
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GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2020Co-Authors: Chia-chun Tsai, Jan-ou WuAbstract:This study has demonstrated that the clock tree construction in an SoC should be expanded to consider the intrinsic delay and skew of each IP's clock sink. A novel algorithm, called GDME, is proposed to combine grey relational clustering and DME approach for solving the problem of clock tree construction. Grey relational analysis can cluster the best pair of clock sinks and that guide a Tapping Point search for a DME algorithm for constructing a clock tree with zero skew and minimal delay. Experimentally, the proposed algorithm always obtains an RC-or RLC-based clock tree with zero skew and minimal delay for all the test cases and benchmarks. Experimental results demonstrate that the GDME improves up to 3.74% for total average in terms of total wire length compared with other DME algorithms. Furthermore, our results for the zero-skew RLC-based clock trees compared with Hspice are 0.017% and 0.2% lower for absolute average in terms of skew and delay, respectively.
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X-architecture clock tree construction associated with buffer insertion and sizing
2009 1st Asia Symposium on Quality Electronic Design, 2009Co-Authors: Chia-chun Tsai, Jan-ou WuAbstract:Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching method for paired Points is applied to determine Tapping Points and simplify the merging procedure of DME approach. Next, Two unit-size buffers are respectively inserted into two branches of a Tapping Point and then the sizes of buffers are adjusted to minimize two branch delays. Moreover, X-flip and wire sizing techniques are sequentially applied to shorten wire length and keep zero skew. Given a set of n clock sinks and a B-type buffer library, the proposed algorithm can obtain a buffered X-architecture zero skew clock tree with minimal delay and power consumption in O(B2nlogn). Experimental results on benchmarks compared with other bufferless X-routing algorithms show the improvements of 98.9%, 1.4%, 90.2%, and 90.2% in terms of clock delay, wire length, downstream capacitance, and power consumption, respectively.
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APCCAS - Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Chia-chun Tsai, Jan-ou Wu, Yu-ting ShiehAbstract:In this paper, the authors propose a new numerical method of Tapping Point search based on uniformly distributed RLC wire model. A Tapping Point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree. The approach can be associated with DME or MMM approach to construct an exact zero-skew clock tree. MCNC benchmarks are evaluated by our algorithm and the simulations of using the Tapping Point binary search and Hspice are for the comparison. Experimental results show that it always gets zero-skew clock trees and the running time also provides pretty fast
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Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Chia-chun Tsai, Jan-ou Wu, Yu-ting ShiehAbstract:In this paper, the authors propose a new numerical method of Tapping Point search based on uniformly distributed RLC wire model. A Tapping Point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree. The approach can be associated with DME or MMM approach to construct an exact zero-skew clock tree. MCNC benchmarks are evaluated by our algorithm and the simulations of using the Tapping Point binary search and Hspice are for the comparison. Experimental results show that it always gets zero-skew clock trees and the running time also provides pretty fast
Chia-chun Tsai - One of the best experts on this subject based on the ideXlab platform.
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GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2020Co-Authors: Chia-chun Tsai, Jan-ou WuAbstract:This study has demonstrated that the clock tree construction in an SoC should be expanded to consider the intrinsic delay and skew of each IP's clock sink. A novel algorithm, called GDME, is proposed to combine grey relational clustering and DME approach for solving the problem of clock tree construction. Grey relational analysis can cluster the best pair of clock sinks and that guide a Tapping Point search for a DME algorithm for constructing a clock tree with zero skew and minimal delay. Experimentally, the proposed algorithm always obtains an RC-or RLC-based clock tree with zero skew and minimal delay for all the test cases and benchmarks. Experimental results demonstrate that the GDME improves up to 3.74% for total average in terms of total wire length compared with other DME algorithms. Furthermore, our results for the zero-skew RLC-based clock trees compared with Hspice are 0.017% and 0.2% lower for absolute average in terms of skew and delay, respectively.
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X-architecture clock tree construction associated with buffer insertion and sizing
2009 1st Asia Symposium on Quality Electronic Design, 2009Co-Authors: Chia-chun Tsai, Jan-ou WuAbstract:Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching method for paired Points is applied to determine Tapping Points and simplify the merging procedure of DME approach. Next, Two unit-size buffers are respectively inserted into two branches of a Tapping Point and then the sizes of buffers are adjusted to minimize two branch delays. Moreover, X-flip and wire sizing techniques are sequentially applied to shorten wire length and keep zero skew. Given a set of n clock sinks and a B-type buffer library, the proposed algorithm can obtain a buffered X-architecture zero skew clock tree with minimal delay and power consumption in O(B2nlogn). Experimental results on benchmarks compared with other bufferless X-routing algorithms show the improvements of 98.9%, 1.4%, 90.2%, and 90.2% in terms of clock delay, wire length, downstream capacitance, and power consumption, respectively.
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APCCAS - Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Chia-chun Tsai, Jan-ou Wu, Yu-ting ShiehAbstract:In this paper, the authors propose a new numerical method of Tapping Point search based on uniformly distributed RLC wire model. A Tapping Point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree. The approach can be associated with DME or MMM approach to construct an exact zero-skew clock tree. MCNC benchmarks are evaluated by our algorithm and the simulations of using the Tapping Point binary search and Hspice are for the comparison. Experimental results show that it always gets zero-skew clock trees and the running time also provides pretty fast
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Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Chia-chun Tsai, Jan-ou Wu, Yu-ting ShiehAbstract:In this paper, the authors propose a new numerical method of Tapping Point search based on uniformly distributed RLC wire model. A Tapping Point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree. The approach can be associated with DME or MMM approach to construct an exact zero-skew clock tree. MCNC benchmarks are evaluated by our algorithm and the simulations of using the Tapping Point binary search and Hspice are for the comparison. Experimental results show that it always gets zero-skew clock trees and the running time also provides pretty fast
Yu-ting Shieh - One of the best experts on this subject based on the ideXlab platform.
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APCCAS - Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Chia-chun Tsai, Jan-ou Wu, Yu-ting ShiehAbstract:In this paper, the authors propose a new numerical method of Tapping Point search based on uniformly distributed RLC wire model. A Tapping Point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree. The approach can be associated with DME or MMM approach to construct an exact zero-skew clock tree. MCNC benchmarks are evaluated by our algorithm and the simulations of using the Tapping Point binary search and Hspice are for the comparison. Experimental results show that it always gets zero-skew clock trees and the running time also provides pretty fast
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Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Chia-chun Tsai, Jan-ou Wu, Yu-ting ShiehAbstract:In this paper, the authors propose a new numerical method of Tapping Point search based on uniformly distributed RLC wire model. A Tapping Point for two subtrees based on the numerical analysis of the model is always determined for exact zero skew. With the bottom-up recursion, the characteristic of zero skew upward propagation for two hierarchical subtrees is proved for a multi-level clock tree. The approach can be associated with DME or MMM approach to construct an exact zero-skew clock tree. MCNC benchmarks are evaluated by our algorithm and the simulations of using the Tapping Point binary search and Hspice are for the comparison. Experimental results show that it always gets zero-skew clock trees and the running time also provides pretty fast
Yao-wen Chang - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010Co-Authors: Xin-wei Shih, Chung-chun Cheng, Yuan-kai Ho, Yao-wen ChangAbstract:In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The nominal clock skew always plays a crucial role in determining circuit performance and thus should be a first-order objective for clock-tree synthesis. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clock Network Synthesis Contest as the major optimization objective to measure the effects of process variation on clock-tree synthesis. In this paper, we propose a three-level framework which effectively constructs clock trees by performing blockage-avoiding buffer insertion with both nominal skew and CLR minimization. To cope with the objectives, we present a novel three-stage TTR clock-tree construction algorithm which consists of clock-tree Topology Generation, Tapping-Point Determination, and Routing. Experimental results show that our framework with the TTR algorithm achieves the best average quality for both nominal skew and CLR, compared to all the participating teams for the 2009 ISPD Clock Network Synthesis Contest.
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Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010Co-Authors: Xin-wei Shih, Chung-chun Cheng, Yuan-kai Ho, Yao-wen ChangAbstract:In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The nominal clock skew always plays a crucial role in determining circuit performance and thus should be a first-order objective for clock-tree synthesis. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clock Network Synthesis Contest as the major optimization objective to measure the effects of process variation on clock-tree synthesis. In this paper, we propose a three-level framework which effectively constructs clock trees by performing blockage-avoiding buffer insertion with both nominal skew and CLR minimization. To cope with the objectives, we present a novel three-stage TTR clock-tree construction algorithm which consists of clock-tree Topology Generation, Tapping-Point Determination, and Routing. Experimental results show that our framework with the TTR algorithm achieves the best average quality for both nominal skew and CLR, compared to all the participating teams for the 2009 ISPD Clock Network Synthesis Contest.
Naonobu Okazaki - One of the best experts on this subject based on the ideXlab platform.
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NBiS - Proposal of Rhythm Authentication Method Using Users Classification by Self-Organizing Map
2015 18th International Conference on Network-Based Information Systems, 2015Co-Authors: Yoshihiro Kita, Mirang Park, Naonobu OkazakiAbstract:The authentication methods, e.g. PINs and patterns, are used on screen lock for mobile devices. These methods are vulnerable to attacks by peeking. This problem is hard to solve, as long as the user input the information of authentication while he/she watches the screen. In this paper, we propose the rhythm authentication method that uses a user classification by the self-organizing map (SOM) using the event times and coordinates of Tapping Point on a screen. This method is not peeked by others, because the user can tap the screen only, and not needs to watch the screen. Therefore, we expect to solve the shoulder-surfing attack vulnerability by our approach.
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Proposal of Rhythm Authentication Method Using Users Classification by Self-Organizing Map
2015 18th International Conference on Network-Based Information Systems, 2015Co-Authors: Yoshihiro Kita, Mirang Park, Naonobu OkazakiAbstract:The authentication methods, e.g. PINs and patterns, are used on screen lock for mobile devices. These methods are vulnerable to attacks by peeking. This problem is hard to solve, as long as the user input the information of authentication while he/she watches the screen. In this paper, we propose the rhythm authentication method that uses a user classification by the self-organizing map (SOM) using the event times and coordinates of Tapping Point on a screen. This method is not peeked by others, because the user can tap the screen only, and not needs to watch the screen. Therefore, we expect to solve the shoulder-surfing attack vulnerability by our approach.
