The Experts below are selected from a list of 32649 Experts worldwide ranked by ideXlab platform
Marios C Papaefthymiou  One of the best experts on this subject based on the ideXlab platform.

A clock Tree Topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001CoAuthors: Dimitrios Velenis, E.g. Friedman, Marios C PapaefthymiouAbstract:The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock Tree Topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.

ISCAS (4)  A clock Tree Topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1CoAuthors: Dimitrios Velenis, E.g. Friedman, Marios C PapaefthymiouAbstract:The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock Tree Topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.
Enno Ohlebusch  One of the best experts on this subject based on the ideXlab platform.

SpaceEfficient Parallel Construction of Succinct Representations of Suffix Tree Topologies
ACM Journal of Experimental Algorithmics, 2017CoAuthors: Uwe Baier, Timo Beller, Enno OhlebuschAbstract:A compressed suffix Tree usually consists of three components: a compressed suffix array, a compressed LCParray, and a succinct representation of the suffix Tree Topology. There are parallel algorithms that construct the suffix array and the LCParray, but none for the third component. In this article, we present parallel algorithms on shared memory architectures that construct the balanced parentheses sequence (BPS), an explicit succinct representation of the suffix Tree Topology, as well as the enhanced balanced parentheses representation (eBPR), an implicit succinct representation of the suffix Tree Topology. For both representations, this article presents a sequential construction algorithm (a new one for the BPS), a linear work and O(log n) time parallel construction algorithm, and a heuristic parallel construction algorithm that works very well in practice. The experimental results show that our methods are well suited for realworld applications.

SPIRE  Parallel Construction of Succinct Representations of Suffix Tree Topologies
String Processing and Information Retrieval, 2015CoAuthors: Uwe Baier, Timo Beller, Enno OhlebuschAbstract:A compressed suffix Tree usually consists of three components: a compressed suffix array, a compressed $$\mathsf {LCP}$$array, and a succinct representation of the suffix Tree Topology. There are parallel algorithms that construct the suffix array and the $$\mathsf {LCP}$$array, but none for the third component. In this paper, we present parallel algorithms on shared memory architectures that construct the enhanced balanced parentheses representation $$\mathsf {BPR}$$. The enhanced $$\mathsf {BPR}$$ is an implicit succinct representation of the suffix Tree Topology, which supports all navigational operations on the suffix Tree. It can also be used to efficiently construct the $$\mathsf {BPS}$$, an explicit succinct representation of the suffix Tree Topology.
Dimitrios Velenis  One of the best experts on this subject based on the ideXlab platform.

A clock Tree Topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001CoAuthors: Dimitrios Velenis, E.g. Friedman, Marios C PapaefthymiouAbstract:The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock Tree Topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.

ISCAS (4)  A clock Tree Topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1CoAuthors: Dimitrios Velenis, E.g. Friedman, Marios C PapaefthymiouAbstract:The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock Tree Topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.
Uwe Baier  One of the best experts on this subject based on the ideXlab platform.

SpaceEfficient Parallel Construction of Succinct Representations of Suffix Tree Topologies
ACM Journal of Experimental Algorithmics, 2017CoAuthors: Uwe Baier, Timo Beller, Enno OhlebuschAbstract:A compressed suffix Tree usually consists of three components: a compressed suffix array, a compressed LCParray, and a succinct representation of the suffix Tree Topology. There are parallel algorithms that construct the suffix array and the LCParray, but none for the third component. In this article, we present parallel algorithms on shared memory architectures that construct the balanced parentheses sequence (BPS), an explicit succinct representation of the suffix Tree Topology, as well as the enhanced balanced parentheses representation (eBPR), an implicit succinct representation of the suffix Tree Topology. For both representations, this article presents a sequential construction algorithm (a new one for the BPS), a linear work and O(log n) time parallel construction algorithm, and a heuristic parallel construction algorithm that works very well in practice. The experimental results show that our methods are well suited for realworld applications.

SPIRE  Parallel Construction of Succinct Representations of Suffix Tree Topologies
String Processing and Information Retrieval, 2015CoAuthors: Uwe Baier, Timo Beller, Enno OhlebuschAbstract:A compressed suffix Tree usually consists of three components: a compressed suffix array, a compressed $$\mathsf {LCP}$$array, and a succinct representation of the suffix Tree Topology. There are parallel algorithms that construct the suffix array and the $$\mathsf {LCP}$$array, but none for the third component. In this paper, we present parallel algorithms on shared memory architectures that construct the enhanced balanced parentheses representation $$\mathsf {BPR}$$. The enhanced $$\mathsf {BPR}$$ is an implicit succinct representation of the suffix Tree Topology, which supports all navigational operations on the suffix Tree. It can also be used to efficiently construct the $$\mathsf {BPS}$$, an explicit succinct representation of the suffix Tree Topology.
E.g. Friedman  One of the best experts on this subject based on the ideXlab platform.

A clock Tree Topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001CoAuthors: Dimitrios Velenis, E.g. Friedman, Marios C PapaefthymiouAbstract:The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock Tree Topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.

ISCAS (4)  A clock Tree Topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1CoAuthors: Dimitrios Velenis, E.g. Friedman, Marios C PapaefthymiouAbstract:The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock Tree Topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented.