The Experts below are selected from a list of 7236 Experts worldwide ranked by ideXlab platform
Colm J. Prendergast - One of the best experts on this subject based on the ideXlab platform.
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A PAL/NTSC digital video encoder on 0.6-/spl mu/m CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2/spl deg/ differential phase
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Timothy J. Cummins, Brian P Murray, Colm J. PrendergastAbstract:A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.
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a pal ntsc digital video encoder on 0 6 spl mu m cmos with 66 db typical snr 0 4 differential gain and 0 2 spl deg differential phase
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Timothy J. Cummins, Brian P Murray, Colm J. PrendergastAbstract:A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.
Timothy J. Cummins - One of the best experts on this subject based on the ideXlab platform.
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A PAL/NTSC digital video encoder on 0.6-/spl mu/m CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2/spl deg/ differential phase
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Timothy J. Cummins, Brian P Murray, Colm J. PrendergastAbstract:A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.
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a pal ntsc digital video encoder on 0 6 spl mu m cmos with 66 db typical snr 0 4 differential gain and 0 2 spl deg differential phase
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Timothy J. Cummins, Brian P Murray, Colm J. PrendergastAbstract:A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.
Brian P Murray - One of the best experts on this subject based on the ideXlab platform.
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A PAL/NTSC digital video encoder on 0.6-/spl mu/m CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2/spl deg/ differential phase
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Timothy J. Cummins, Brian P Murray, Colm J. PrendergastAbstract:A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.
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a pal ntsc digital video encoder on 0 6 spl mu m cmos with 66 db typical snr 0 4 differential gain and 0 2 spl deg differential phase
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Timothy J. Cummins, Brian P Murray, Colm J. PrendergastAbstract:A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2/spl deg/, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4/spl times/4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7/spl times/7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 /spl mu/W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, /spl Theta/ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70/spl deg/C.
Oussama Bazzi - One of the best experts on this subject based on the ideXlab platform.
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EVM Closed-Form Expression for OFDM Signals With Tone Reservation-Based PAPR Reduction
IEEE Transactions on Wireless Communications, 2020Co-Authors: Mariam El Hassan, Matthieu Crussière, Jean-françois Hélard, Youssef Nasser, Oussama BazziAbstract:Peak to average power ratio (PAPR) reduction of OFDM signals has extensively been studied in the literature. Tone Reservation (TR) is one of the most famous algorithms and has already been included in some digital Television Standards such as DVB-T2 and ASTC3.0. However, the literature is still lacking theoretical analysis and performance bounds for the PAPR reduction of OFDM signals, especially using TR algorithms. For the first time, this paper provides fundamental results establishing the links between TR-PAPR reduction and the remaining signal distortions at the output of a non-linear high power amplifier (HPA) with and without memory effects. We first derive a generic EVM expression relying on the statistical characteristics of the samples composing the time domain signal and for any PAPR reduction technique. Computing these moments in the case of the quadratically constrained quadratic problem (QCQP) algorithm known as the optimal solution to the TR-PAPR reduction problem allows us to get the lower bound of the EVM of OFDM signals after TR-PAPR reduction and non-linear HPA. As a reference, we also provide the EVM expression using a clipping-based PAPR reduction method. The obtained EVM expressions have direct practical meaning since they are in function of the input power back-off (IBO) applied to the signal before the HPA. They also consist in a general analytical framework for OFDM PAPR reduction since they can be further exploited to analyze the performance of sub-optimal TR-based PAPR reduction algorithms.
H. Niwa - One of the best experts on this subject based on the ideXlab platform.
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Video tape recorder with digital Television Standards converter
IEEE Transactions on Consumer Electronics, 1990Co-Authors: M. Tomita, T. Ohtsuki, S. Ogata, H. NiwaAbstract:A recently developed worldwide video tape recorder (VTR) with a digital Television Standards converter is described. The recorder can record and playback all VHS formats corresponding to each of the world's TV Standards such as NTSC, PAL and SECAM.
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WPM-7.4 VIDEO TAPE RECORDER WITH DIGITAL Television Standards CONVERTER
1990Co-Authors: M. Tomita, T. Ohtsuki, Sigeru Ogataa, H. NiwaAbstract:between these formats include the tape format, the rotation speed of the video head and the pe$eveloped worldwide video tape color signal processing. In VHS standard VTRs, recorder with a digital Television Standards there are six of these different formats. converter is described. The recorder can record and playback all VHS formats corresponding to each of the world’s TV Standards such as NTSC, PAL and SECAM?% i
