The Experts below are selected from a list of 207 Experts worldwide ranked by ideXlab platform
Zensho Nakao - One of the best experts on this subject based on the ideXlab platform.
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An Efficient Specification for System Verification
Journal of Advanced Computational Intelligence and Intelligent Informatics, 2006Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:In design of complex and large scale systems, system verification has played an important role. In this article, we focus on specification process of model checking in system verifications. Modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which specifications with Temporal Formulas are obtained inductively. We will show verification results using the proposed Temporal Formula specification method, and show that amount of memory, OBDD nodes, and execution time are reduced.
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an efficient Temporal Formula specification method for system verification
ISIS 2005 PROCEEDINGS OF THE 6TH SYMPOSIUM ON ADVANCED INTELLIGENT SYSTEMS, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on specification process of model checking. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which Temporal Formulas are obtained inductively, and amounts of memory, OBDD nodes, and execution time are reduced. We will show verification results using the proposed a Temporal Formula specification method.
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Inductive Temporal Formula Specifications for System Verification
Journal of Advanced Computational Intelligence and Intelligent Informatics, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on model checking methods. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method Temporal Formulas are obtained inductively, and amounts of memory and time are reduced. We will show verification results using the proposed method.
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An Efficient Temporal Formula Specification Method for Asynchronous Concurrent Systems
TENCON 2005 - 2005 IEEE Region 10 Conference, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. System verification ascertains whether designed systems can be executed or specified. Symbolic model checker SMV is widely-used for the verification. In this article, we focus on specification process of model checking for the SMV. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which Temporal Formulas are obtained inductively, and amounts of memory, OBDD nodes, and execution time are reduced. We will show verification results using the proposed a Temporal Formula specification method by some benchmark examples.
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Inductive Temporal Formula specifications
2004 IEEE Region 10 Conference TENCON 2004., 1Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on model checking methods. Behaviors of modeled systems are in general specified in terms of Temporal Formulas of computation tree logic and users must have enough knowledge of Temporal specification because the specification might be complex. We propose a method through which Temporal Formulas are obtained inductively and amounts of required memory and time are reduced. We will show verification results which are obtained by the proposed method.
Chikatoshi Yamada - One of the best experts on this subject based on the ideXlab platform.
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Temporal Formula specifications of asynchronous control module in model checking
2006Co-Authors: Chikatoshi Yamada, Yasunori NagataAbstract:System verification plays an important role in large scale and complex systems. However, it is very difficult for designers other than the specialist who is well versed in Temporal Logic to specify behaviors of the system. This article considers the case where designers of systems can specify Temporal Formulas easily in system verification. We propose a method by which Temporal Formulas can be obtained inductively for specifications in system verification. System designers can easily derive complex Temporal Formulas by using the specification method.
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An Efficient Specification for System Verification
Journal of Advanced Computational Intelligence and Intelligent Informatics, 2006Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:In design of complex and large scale systems, system verification has played an important role. In this article, we focus on specification process of model checking in system verifications. Modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which specifications with Temporal Formulas are obtained inductively. We will show verification results using the proposed Temporal Formula specification method, and show that amount of memory, OBDD nodes, and execution time are reduced.
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an efficient Temporal Formula specification method for system verification
ISIS 2005 PROCEEDINGS OF THE 6TH SYMPOSIUM ON ADVANCED INTELLIGENT SYSTEMS, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on specification process of model checking. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which Temporal Formulas are obtained inductively, and amounts of memory, OBDD nodes, and execution time are reduced. We will show verification results using the proposed a Temporal Formula specification method.
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Inductive Temporal Formula Specifications for System Verification
Journal of Advanced Computational Intelligence and Intelligent Informatics, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on model checking methods. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method Temporal Formulas are obtained inductively, and amounts of memory and time are reduced. We will show verification results using the proposed method.
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An Efficient Temporal Formula Specification Method for Asynchronous Concurrent Systems
TENCON 2005 - 2005 IEEE Region 10 Conference, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. System verification ascertains whether designed systems can be executed or specified. Symbolic model checker SMV is widely-used for the verification. In this article, we focus on specification process of model checking for the SMV. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which Temporal Formulas are obtained inductively, and amounts of memory, OBDD nodes, and execution time are reduced. We will show verification results using the proposed a Temporal Formula specification method by some benchmark examples.
Amir Pnueli - One of the best experts on this subject based on the ideXlab platform.
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FM - PSL model checking and run-time verification via testers
FM 2006: Formal Methods, 2006Co-Authors: Amir Pnueli, A. ZaksAbstract:The paper introduces the construct of Temporal testers as a compositional basis for the construction of automata corresponding to Temporal Formulas in the PSL logic. Temporal testers can be viewed as (non-deterministic) transducers that, at any point, output a boolean value which is 1 iff the corresponding Temporal Formula holds starting at the current position. The main advantage of testers, compared to acceptors (such as Buchi automata) is that they are compositional. Namely, a tester for a compound Formula can be constructed out of the testers for its sub-Formulas. In this paper, we extend the application of the testers method from LTL to the logic PSL. Besides providing the construction of testers for PSL, we indicate how the symbolic representation of the testers can be directly utilized for efficient model checking and run-time monitoring
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Control and data abstraction: the cornerstones of practical formal verification
International Journal on Software Tools for Technology Transfer, 2000Co-Authors: Yonit Kesten, Amir PnueliAbstract:In spite of the impressive progress in the development of the two main methods for formal verification of reactive systems – Symbolic Model Checking and Deductive Verification, they are still limited in their ability to handle large systems. It is generally recognized that the only way these methods can ever scale up is by the extensive use of abstraction and modularization, which break the task of verifying a large system into several smaller tasks of verifying simpler systems. In this paper, we review the two main tools of compositionality and abstraction in the framework of linear Temporal logic. We illustrate the application of these two methods for the reduction of an infinite-state system into a finite-state system that can then be verified using model checking. The technical contributions contained in this paper are a full Formulation of abstraction when applied to a system with both weak and strong fairness requirements and to a general Temporal Formula, and a presentation of a compositional framework for shared variables and its application for forming network invariants .
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25 Years of Model Checking - On the Merits of Temporal Testers
25 Years of Model Checking, 1Co-Authors: Amir Pnueli, A. ZaksAbstract:The paper discusses the merits of Temporal testers, which can serve as a compositional basis for automata construction corresponding to Temporal Formulas in the context of ltl , psl , and mitl logics. Temporal testers can be viewed as (non-deterministic) transducers that, at any point, output a boolean value which is 1 iff the corresponding Temporal Formula holds starting at the current position. The main advantage of testers, compared to acceptors (such asBuchi automata) is their compositionality. Namely, a tester for a compound Formula can be constructed out of the testers for its sub-Formulas. Besides providing the construction of testers for Formulas specified in ltl , psl , and mitl , the paper also presents a general overview of the tester methodology, and highlights some of the unique features and applications of transducers including compositional deductive verification of ltl properties.
Yasunori Nagata - One of the best experts on this subject based on the ideXlab platform.
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Temporal Formula specifications of asynchronous control module in model checking
2006Co-Authors: Chikatoshi Yamada, Yasunori NagataAbstract:System verification plays an important role in large scale and complex systems. However, it is very difficult for designers other than the specialist who is well versed in Temporal Logic to specify behaviors of the system. This article considers the case where designers of systems can specify Temporal Formulas easily in system verification. We propose a method by which Temporal Formulas can be obtained inductively for specifications in system verification. System designers can easily derive complex Temporal Formulas by using the specification method.
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An Efficient Specification for System Verification
Journal of Advanced Computational Intelligence and Intelligent Informatics, 2006Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:In design of complex and large scale systems, system verification has played an important role. In this article, we focus on specification process of model checking in system verifications. Modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which specifications with Temporal Formulas are obtained inductively. We will show verification results using the proposed Temporal Formula specification method, and show that amount of memory, OBDD nodes, and execution time are reduced.
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an efficient Temporal Formula specification method for system verification
ISIS 2005 PROCEEDINGS OF THE 6TH SYMPOSIUM ON ADVANCED INTELLIGENT SYSTEMS, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on specification process of model checking. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which Temporal Formulas are obtained inductively, and amounts of memory, OBDD nodes, and execution time are reduced. We will show verification results using the proposed a Temporal Formula specification method.
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Inductive Temporal Formula Specifications for System Verification
Journal of Advanced Computational Intelligence and Intelligent Informatics, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. In this article, we focus on model checking methods. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method Temporal Formulas are obtained inductively, and amounts of memory and time are reduced. We will show verification results using the proposed method.
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An Efficient Temporal Formula Specification Method for Asynchronous Concurrent Systems
TENCON 2005 - 2005 IEEE Region 10 Conference, 2005Co-Authors: Chikatoshi Yamada, Yasunori Nagata, Zensho NakaoAbstract:Design verification has played an important role in the design of large scale and complex systems. System verification ascertains whether designed systems can be executed or specified. Symbolic model checker SMV is widely-used for the verification. In this article, we focus on specification process of model checking for the SMV. Behaviors of modeled systems are in general specified by Temporal Formulas of computation tree logic, and users must know well about Temporal specification because the specification might be complex. We propose a method by which Temporal Formulas are obtained inductively, and amounts of memory, OBDD nodes, and execution time are reduced. We will show verification results using the proposed a Temporal Formula specification method by some benchmark examples.
Josef Widder - One of the best experts on this subject based on the ideXlab platform.
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a short counterexample property for safety and liveness verification of fault tolerant distributed algorithms
Symposium on Principles of Programming Languages, 2017Co-Authors: Igor Konnov, Marijana Lazic, Helmut Veith, Josef WidderAbstract:Distributed algorithms have many mission-critical applications ranging from embedded systems and replicated databases to cloud computing. Due to asynchronous communication, process faults, or network failures, these algorithms are difficult to design and verify. Many algorithms achieve fault tolerance by using threshold guards that, for instance, ensure that a process waits until it has received an acknowledgment from a majority of its peers. Consequently, domain-specific languages for fault-tolerant distributed systems offer language support for threshold guards. We introduce an automated method for model checking of safety and liveness of threshold-guarded distributed algorithms in systems where the number of processes and the fraction of faulty processes are parameters. Our method is based on a short counterexample property: if a distributed algorithm violates a Temporal specification (in a fragment of LTL), then there is a counterexample whose length is bounded and independent of the parameters. We prove this property by (i) characterizing executions depending on the structure of the Temporal Formula, and (ii) using commutativity of transitions to accelerate and shorten executions. We extended the ByMC toolset (Byzantine Model Checker) with our technique, and verified liveness and safety of 10 prominent fault-tolerant distributed algorithms, most of which were out of reach for existing techniques.
