The Experts below are selected from a list of 2517 Experts worldwide ranked by ideXlab platform
David Brooks - One of the best experts on this subject based on the ideXlab platform.
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voltage smoothing characterizing and mitigating voltage noise in production processors via software guided Thread scheduling
International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
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MICRO - Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, Wonyoung Kim, Gu-yeon Wei, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
Vijay Janapa Reddi - One of the best experts on this subject based on the ideXlab platform.
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voltage smoothing characterizing and mitigating voltage noise in production processors via software guided Thread scheduling
International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
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MICRO - Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, Wonyoung Kim, Gu-yeon Wei, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
Svilen Kanev - One of the best experts on this subject based on the ideXlab platform.
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voltage smoothing characterizing and mitigating voltage noise in production processors via software guided Thread scheduling
International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
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MICRO - Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, Wonyoung Kim, Gu-yeon Wei, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
Michael D Smith - One of the best experts on this subject based on the ideXlab platform.
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voltage smoothing characterizing and mitigating voltage noise in production processors via software guided Thread scheduling
International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
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MICRO - Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, Wonyoung Kim, Gu-yeon Wei, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
Simone Campanoni - One of the best experts on this subject based on the ideXlab platform.
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voltage smoothing characterizing and mitigating voltage noise in production processors via software guided Thread scheduling
International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
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MICRO - Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
2010 43rd Annual IEEE ACM International Symposium on Microarchitecture, 2010Co-Authors: Vijay Janapa Reddi, Svilen Kanev, Simone Campanoni, Michael D Smith, Wonyoung Kim, Gu-yeon Wei, David BrooksAbstract:Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-Threaded, multi-Threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4 percent, far from the processor's 14percent worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15 percent to 20 percent performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing micro architectural activity that leads to voltage swings within multi-core systems, we show that a voltage-noise-aware Thread Scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
