The Experts below are selected from a list of 78 Experts worldwide ranked by ideXlab platform

Mark Horowitz - One of the best experts on this subject based on the ideXlab platform.

  • 3- 1 A 50 Gb/s 32 x 32 CMOS Crossbar Chip using Asymmetric Serial Links*
    2013
    Co-Authors: Kun-yung Ken Chang, Shang-tse Chuang, Nick Mckeown, Mark Horowitz
    Abstract:

    A 32 x 32 synchronous crossbar chip was designed in a 0.27pm CMOS technology for use in a high-speed network switch [I]. The crossbar chip uses 32 Asymmetric Serial Links [2][3] to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexors with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is < when all channels and the switch core are operating. The crossbar chip consumes 5W and provides a total bandwidth above 50 Gb/s. Architecture Crossbar switches are increasingly used for high capacity network switches [I]. Using high-speed serial links for the YO interface of a crossbar switch chip can reduce the number of VO pins required to provide a given bandwidth. A crossbar chip, which has many links converging on it, tends to be large and power-hungry because of the F silicon area and power consumed by the Timing Circuits (usually PLLs) and transceivers. To reduce both power and area, we used Asymmetric Serial Links, which adjust the transmitter and receiver clocks on the port chips (the Smart End of the link) while leaving the clocks on the crossbar chip (the Dumb End) fixed. Each crossbar chip interfaces with as many as 32 network port chips in our design. AS

  • A 50 Gb/s 32 × 32 CMOS Crossbar Chip using Asymmetric Serial Links*
    2008
    Co-Authors: Kun-yung Ken Chang, Shang-tse Chuang, Nick Mckeown, Mark Horowitz
    Abstract:

    A synchronous crossbar chip was designed in a 0.27μm CMOS technology for use in a high-speed network switch [1]. The crossbar chip uses 32 Asymmetric Serial Links [2] [3] to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexors with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is < 10-14 32 × 32 when all channels and the switch core are operating. The crossbar chip consumes 5W and provides a total bandwidth above 50 Gb/s. Architecture Crossbar switches are increasingly used for high capacity network switches [1]. Using high-speed serial links for the I/O interface of a crossbar switch chip can reduce the number of I/O pins required to provide a given bandwidth. A crossbar chip, which has many links converging on it, tends to be large and power-hungry because of the silicon area and power consumed by the Timing Circuits (usually PLLs) and transceivers. To reduce both power and area, we used Asymmetric Serial Links, which adjust the transmitter and receiver clocks on the port chips (the Smart End of the link) while leaving the clocks on the crossbar chip (the Dumb End) fixed. Each crossbar chip interfaces with as many as 32 network port chips in our design. ASL AS

Ra Sporea - One of the best experts on this subject based on the ideXlab platform.

  • Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
    2020
    Co-Authors: Bestelink E, Km Niang, Bairaktaris G, Maiolo L, Maita F, Ali K, Aj Flewitt, Silva Srp, Ra Sporea
    Abstract:

    © 2001-2012 IEEE. Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore's law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor's unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a two-transistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and Timing Circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers

Sporea Radu - One of the best experts on this subject based on the ideXlab platform.

  • Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Bestelink Eva, Niang, Kham M., Bairaktaris George, Maiolo Luca, Maita Francesco, Ali Kalil, Flewitt, Andrew J., Silva Ravi, Sporea Radu
    Abstract:

    Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and Timing Circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers

Kun-yung Ken Chang - One of the best experts on this subject based on the ideXlab platform.

  • 3- 1 A 50 Gb/s 32 x 32 CMOS Crossbar Chip using Asymmetric Serial Links*
    2013
    Co-Authors: Kun-yung Ken Chang, Shang-tse Chuang, Nick Mckeown, Mark Horowitz
    Abstract:

    A 32 x 32 synchronous crossbar chip was designed in a 0.27pm CMOS technology for use in a high-speed network switch [I]. The crossbar chip uses 32 Asymmetric Serial Links [2][3] to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexors with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is < when all channels and the switch core are operating. The crossbar chip consumes 5W and provides a total bandwidth above 50 Gb/s. Architecture Crossbar switches are increasingly used for high capacity network switches [I]. Using high-speed serial links for the YO interface of a crossbar switch chip can reduce the number of VO pins required to provide a given bandwidth. A crossbar chip, which has many links converging on it, tends to be large and power-hungry because of the F silicon area and power consumed by the Timing Circuits (usually PLLs) and transceivers. To reduce both power and area, we used Asymmetric Serial Links, which adjust the transmitter and receiver clocks on the port chips (the Smart End of the link) while leaving the clocks on the crossbar chip (the Dumb End) fixed. Each crossbar chip interfaces with as many as 32 network port chips in our design. AS

  • A 50 Gb/s 32 × 32 CMOS Crossbar Chip using Asymmetric Serial Links*
    2008
    Co-Authors: Kun-yung Ken Chang, Shang-tse Chuang, Nick Mckeown, Mark Horowitz
    Abstract:

    A synchronous crossbar chip was designed in a 0.27μm CMOS technology for use in a high-speed network switch [1]. The crossbar chip uses 32 Asymmetric Serial Links [2] [3] to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexors with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is < 10-14 32 × 32 when all channels and the switch core are operating. The crossbar chip consumes 5W and provides a total bandwidth above 50 Gb/s. Architecture Crossbar switches are increasingly used for high capacity network switches [1]. Using high-speed serial links for the I/O interface of a crossbar switch chip can reduce the number of I/O pins required to provide a given bandwidth. A crossbar chip, which has many links converging on it, tends to be large and power-hungry because of the silicon area and power consumed by the Timing Circuits (usually PLLs) and transceivers. To reduce both power and area, we used Asymmetric Serial Links, which adjust the transmitter and receiver clocks on the port chips (the Smart End of the link) while leaving the clocks on the crossbar chip (the Dumb End) fixed. Each crossbar chip interfaces with as many as 32 network port chips in our design. ASL AS

Bestelink E - One of the best experts on this subject based on the ideXlab platform.

  • Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
    2020
    Co-Authors: Bestelink E, Km Niang, Bairaktaris G, Maiolo L, Maita F, Ali K, Aj Flewitt, Silva Srp, Ra Sporea
    Abstract:

    © 2001-2012 IEEE. Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore's law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor's unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a two-transistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and Timing Circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers