The Experts below are selected from a list of 32187 Experts worldwide ranked by ideXlab platform
Yiran Chen - One of the best experts on this subject based on the ideXlab platform.
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loadsa a yield driven Top down Design method for stt ram array
Asia and South Pacific Design Automation Conference, 2013Co-Authors: Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran ChenAbstract:As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great Design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system Designs. Also, the conventional bottom-up Design method incurs costly iterations in the STT-RAM Design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven Top-down Design method to explore the Design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a Top-down Design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level Design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early Design stage of memory or micro-architecture by eliminating the Design integrations, while offering a full statistical view of the Design even when the common yield enhancement practices are applied.
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ASP-DAC - Loadsa: A yield-driven Top-down Design method for STT-RAM array
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran ChenAbstract:As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great Design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system Designs. Also, the conventional bottom-up Design method incurs costly iterations in the STT-RAM Design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven Top-down Design method to explore the Design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a Top-down Design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level Design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early Design stage of memory or micro-architecture by eliminating the Design integrations, while offering a full statistical view of the Design even when the common yield enhancement practices are applied.
Wujie Wen - One of the best experts on this subject based on the ideXlab platform.
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loadsa a yield driven Top down Design method for stt ram array
Asia and South Pacific Design Automation Conference, 2013Co-Authors: Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran ChenAbstract:As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great Design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system Designs. Also, the conventional bottom-up Design method incurs costly iterations in the STT-RAM Design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven Top-down Design method to explore the Design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a Top-down Design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level Design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early Design stage of memory or micro-architecture by eliminating the Design integrations, while offering a full statistical view of the Design even when the common yield enhancement practices are applied.
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ASP-DAC - Loadsa: A yield-driven Top-down Design method for STT-RAM array
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran ChenAbstract:As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great Design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system Designs. Also, the conventional bottom-up Design method incurs costly iterations in the STT-RAM Design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven Top-down Design method to explore the Design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a Top-down Design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level Design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early Design stage of memory or micro-architecture by eliminating the Design integrations, while offering a full statistical view of the Design even when the common yield enhancement practices are applied.
Pablo Gervás - One of the best experts on this subject based on the ideXlab platform.
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A Top-down Design Methodology based on Causality and Chronology for Developing Assisted Story Generation Systems
Proceedings of the 8th ACM conference on Creativity and cognition, 2011Co-Authors: Carlos León, Pablo GervásAbstract:Assisted story generation systems do not include automatic generation of content due to the fact that creating generation algorithms is a challenging task, usually carried out in research projects on Artificial Intelligence. This paper proposes a Top-down Design methodology in which the knowledge representation is based on causality and chronology. The proposed methodology partially eases the process by dividing the narrative generation system in two parts: a generic engine and a domain definition based only on a specific set of predicates. The theoretical model and an implemented case study with resulting stories are presented.
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Creativity & Cognition - A Top-down Design methodology based on causality and chronology for developing assisted story generation systems
Proceedings of the 8th ACM conference on Creativity and cognition - C&C '11, 2011Co-Authors: Carlos León, Pablo GervásAbstract:Assisted story generation systems do not include automatic generation of content due to the fact that creating generation algorithms is a challenging task, usually carried out in research projects on Artificial Intelligence. This paper proposes a Top-down Design methodology in which the knowledge representation is based on causality and chronology. The proposed methodology partially eases the process by dividing the narrative generation system in two parts: a generic engine and a domain definition based only on a specific set of predicates. The theoretical model and an implemented case study with resulting stories are presented.
Hermann Kaindl - One of the best experts on this subject based on the ideXlab platform.
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a case study of systematic Top down Design of cyber physical models with integrated validation and formal verification
ACM Symposium on Applied Computing, 2019Co-Authors: Christoph Luckeneder, Hermann KaindlAbstract:Abstract models are required to handle the complexity for Designing and verifying large-scale systems. An open problem is to consistently and systematically derive a more concrete model from an abstract model with regard to verification of its behavior against certain properties. Based on our recently proposed workflow for systematic Top-down Design of models of a Cyber-physical System (CPS), we present an in-depth case study of Adaptive Cruise Control (ACC). It includes both verification through model checking and validation in the sense that a refined model is checked for its fit with reality. This approach works Top-down for Designing a concrete model by starting from an abstract model. The resulting concrete model was validated and indirectly verified in this case study. In addition, we made a cross-check by verifying it directly on the concrete level. Hence, our case study provides some empirical evidence on the feasibility of this new workflow for Top-down Design of models.
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SAC - A case study of systematic Top-down Design of cyber-physical models with integrated validation and formal verification
Proceedings of the 34th ACM SIGAPP Symposium on Applied Computing, 2019Co-Authors: Christoph Luckeneder, Hermann KaindlAbstract:Abstract models are required to handle the complexity for Designing and verifying large-scale systems. An open problem is to consistently and systematically derive a more concrete model from an abstract model with regard to verification of its behavior against certain properties. Based on our recently proposed workflow for systematic Top-down Design of models of a Cyber-physical System (CPS), we present an in-depth case study of Adaptive Cruise Control (ACC). It includes both verification through model checking and validation in the sense that a refined model is checked for its fit with reality. This approach works Top-down for Designing a concrete model by starting from an abstract model. The resulting concrete model was validated and indirectly verified in this case study. In addition, we made a cross-check by verifying it directly on the concrete level. Hence, our case study provides some empirical evidence on the feasibility of this new workflow for Top-down Design of models.
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systematic Top down Design of cyber physical models with integrated validation and formal verification
International Conference on Software Engineering, 2018Co-Authors: Christoph Luckeneder, Hermann KaindlAbstract:The complexity of Designing and verifying large-scale systems requires abstract models. Consistently and systematically deriving a more concrete model from an abstract model with regard to verification of its behavior against certain properties is an open problem. We propose a new workflow for systematic Top-down Design of models for a Cyber-physical System (CPS). It builds on a theory of systematic abstraction and refinement techniques in the context of verification through model checking. In addition, this workflow includes validation in the sense that a refined model is checked for its fit with reality. Our proposed workflow is new with respect to its systematic determination of model changes on different levels of abstraction based on the V&V results and the formal property over-approximation of an abstract model (as compared to the corresponding concrete model).
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ICSE (Companion Volume) - Systematic Top-down Design of cyber-physical models with integrated validation and formal verification
Proceedings of the 40th International Conference on Software Engineering: Companion Proceeedings, 2018Co-Authors: Christoph Luckeneder, Hermann KaindlAbstract:The complexity of Designing and verifying large-scale systems requires abstract models. Consistently and systematically deriving a more concrete model from an abstract model with regard to verification of its behavior against certain properties is an open problem. We propose a new workflow for systematic Top-down Design of models for a Cyber-physical System (CPS). It builds on a theory of systematic abstraction and refinement techniques in the context of verification through model checking. In addition, this workflow includes validation in the sense that a refined model is checked for its fit with reality. Our proposed workflow is new with respect to its systematic determination of model changes on different levels of abstraction based on the V&V results and the formal property over-approximation of an abstract model (as compared to the corresponding concrete model).
Lu Zhang - One of the best experts on this subject based on the ideXlab platform.
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loadsa a yield driven Top down Design method for stt ram array
Asia and South Pacific Design Automation Conference, 2013Co-Authors: Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran ChenAbstract:As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great Design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system Designs. Also, the conventional bottom-up Design method incurs costly iterations in the STT-RAM Design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven Top-down Design method to explore the Design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a Top-down Design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level Design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early Design stage of memory or micro-architecture by eliminating the Design integrations, while offering a full statistical view of the Design even when the common yield enhancement practices are applied.
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ASP-DAC - Loadsa: A yield-driven Top-down Design method for STT-RAM array
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013Co-Authors: Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran ChenAbstract:As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great Design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system Designs. Also, the conventional bottom-up Design method incurs costly iterations in the STT-RAM Design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven Top-down Design method to explore the Design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a Top-down Design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level Design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early Design stage of memory or micro-architecture by eliminating the Design integrations, while offering a full statistical view of the Design even when the common yield enhancement practices are applied.
