The Experts below are selected from a list of 318327 Experts worldwide ranked by ideXlab platform
Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.
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interactive presentation Logic level fault tolerance approaches targeting nanoelectronics plas
Design Automation and Test in Europe, 2007Co-Authors: Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a Two-Level Logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in Two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wenjing Rao, Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a Two-Level Logic form have placed crossbar-based programmable Logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in Two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
Alex Orailoglu - One of the best experts on this subject based on the ideXlab platform.
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interactive presentation Logic level fault tolerance approaches targeting nanoelectronics plas
Design Automation and Test in Europe, 2007Co-Authors: Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a Two-Level Logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in Two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wenjing Rao, Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a Two-Level Logic form have placed crossbar-based programmable Logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in Two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
Wenjing Rao - One of the best experts on this subject based on the ideXlab platform.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Wenjing Rao, Alex Orailoglu, Ramesh KarriAbstract:A regular structure and capability to implement arbitrary Logic functions in a Two-Level Logic form have placed crossbar-based programmable Logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting Logic tautology in Two-Level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
Hiroshi Imai - One of the best experts on this subject based on the ideXlab platform.
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obdds of a monotone function and of its prime implicants
International Symposium on Algorithms and Computation, 1996Co-Authors: Kazuyoshi Hayase, Hiroshi ImaiAbstract:Coudert made a breakthrough in the Two-Level Logic minimization problem with Ordered Binary Decision Diagrams (OBDDs, in short) recently [3]. This paper discusses relationship between the two OBDDs of a monotone function and of its prime implicant set to clarify the complexity of this practically efficient method. We show that there exists a monotone function which has an O(n) size sum-of-products but cannot be represented by a polynomial size OBDD. In other words, we cannot obtain the OBDD of the prime implicant set of a monotone function in an output-size sensitive manner, once we have constructed the OBDD of that function as in [3], in the worst case. A positive result is also given for a meaningful class of matroid functions.
Giovanni De Micheli - One of the best experts on this subject based on the ideXlab platform.
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multi level Logic benchmarks an exactness study
Asia and South Pacific Design Automation Conference, 2017Co-Authors: Luca Amaru, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierreemmanuel Gaillardon, Giovanni De MicheliAbstract:In this paper, we study exact multi-level Logic benchmarks. We refer to an exact Logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of Logic levels and/or nodes. Exact benchmarks are of paramount importance to design automation because they allow engineers to test the efficiency of heuristic techniques used in practice. When dealing with Two-Level Logic circuits, tools to generate exact benchmarks are available, e.g., espresso-exact, and scale up to relatively large size. However, when moving to modern multi-level Logic circuits, the problem of deriving exact benchmarks is inherently more complex. Indeed, few solutions are known. In this paper, we present a scalable method to generate exact multi-level benchmarks with the optimum, or provably close to the optimum, number of Logic levels. Our technique involves concepts from graph theory and joint support decomposition. Experimental results show an asymptotic exponential gap between state-of-the-art synthesis techniques and our exact results. Our findings underline the need for strong new research in Logic synthesis.
