The Experts below are selected from a list of 153 Experts worldwide ranked by ideXlab platform
Daniel Lavery - One of the best experts on this subject based on the ideXlab platform.
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optimization for the intel spl reg itanium spl reg architecture Register stack
Symposium on Code Generation and Optimization, 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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CGO - Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture Register stack
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
G. Hoflehner - One of the best experts on this subject based on the ideXlab platform.
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optimization for the intel spl reg itanium spl reg architecture Register stack
Symposium on Code Generation and Optimization, 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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CGO - Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture Register stack
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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CGO - Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture Register stack
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Alex Settle, G. Hoflehner, Daniel A Connors, Dan LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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Optimization for the Intel Itanium Architecture Register Stack
IEEE Computer Society, 2003Co-Authors: Alex Settle, G. Hoflehner, Daniel A Connors, Dan LaveryAbstract:The Intel R ○ Itanium R ○ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium R ○ architecture provides a compilercontrollable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium R ○ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium R ○ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches. 1
Daniel A Connors - One of the best experts on this subject based on the ideXlab platform.
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optimization for the intel spl reg itanium spl reg architecture Register stack
Symposium on Code Generation and Optimization, 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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CGO - Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture Register stack
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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CGO - Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture Register stack
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Alex Settle, G. Hoflehner, Daniel A Connors, Dan LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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Optimization for the Intel Itanium Architecture Register Stack
IEEE Computer Society, 2003Co-Authors: Alex Settle, G. Hoflehner, Daniel A Connors, Dan LaveryAbstract:The Intel R ○ Itanium R ○ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium R ○ architecture provides a compilercontrollable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium R ○ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium R ○ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches. 1
Amber Settle - One of the best experts on this subject based on the ideXlab platform.
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optimization for the intel spl reg itanium spl reg architecture Register stack
Symposium on Code Generation and Optimization, 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
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CGO - Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture Register stack
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Amber Settle, G. Hoflehner, Daniel A Connors, Daniel LaveryAbstract:The Intel/spl reg/ Itanium/spl reg/ architecture contains a number of innovative compiler-controllable features designed to exploit instruction level parallelism. New code generation and optimization techniques are critical to the application of these features to improve processor performance. For instance, the Itanium/spl reg/ architecture provides a compiler-controllable Virtual Register stack to reduce the penalty of memory accesses associated with procedure calls. The Itanium/spl reg/ Register Stack Engine (RSE) transparently manages the Register stack and saves and restores physical Registers to and from memory as needed. Existing code generation techniques for the Register stack aggressively allocate Virtual Registers without regard to the Register pressure on different control-flow paths. As such, applications with large data sets may stress the RSE, and cause substantial execution delays due to the high number of Register saves and restores. Since the Itanium/spl reg/ architecture is developed around Explicitly Parallel Instruction Computing (EPIC) concepts, solutions to increasing the Register stack efficiency favor code generation techniques rather than hardware approaches.
Zhaoqing Zhang - One of the best experts on this subject based on the ideXlab platform.
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a Register allocation framework for banked Register files with access constraints
Lecture Notes in Computer Science, 2005Co-Authors: Feng Zhou, Chengyong Wu, Junchao Zhang, Zhaoqing ZhangAbstract:Banked Register file has been proposed to reduce die area, power consumption, and access time. Some embedded processors, e.g. Intel’s IXP network processors, adopt this organization. However, they expose some access constraints in ISA, which complicates the design of Register allocation. In this paper, we present a Register allocation framework for banked Register files with access constraints for the IXP network processors. Our approach relies on the estimation of the costs and benefits of assigning a Virtual Register to a specific bank, as well as that of splitting it into multiple banks via copy instructions. We make the decision of bank assignment or live range splitting based on analysis of these costs and benefits. Compared to previous works, our framework can better balance the Register pressure among multiple banks and improve the performance of typical network applications.
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Asia-Pacific Computer Systems Architecture Conference - A Register allocation framework for banked Register files with access constraints
Lecture Notes in Computer Science, 2005Co-Authors: Feng Zhou, Chengyong Wu, Junchao Zhang, Zhaoqing ZhangAbstract:Banked Register file has been proposed to reduce die area, power consumption, and access time. Some embedded processors, e.g. Intel’s IXP network processors, adopt this organization. However, they expose some access constraints in ISA, which complicates the design of Register allocation. In this paper, we present a Register allocation framework for banked Register files with access constraints for the IXP network processors. Our approach relies on the estimation of the costs and benefits of assigning a Virtual Register to a specific bank, as well as that of splitting it into multiple banks via copy instructions. We make the decision of bank assignment or live range splitting based on analysis of these costs and benefits. Compared to previous works, our framework can better balance the Register pressure among multiple banks and improve the performance of typical network applications.
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inter procedural stacked Register allocation for itanium like architecture
International Conference on Supercomputing, 2003Co-Authors: Liu Yang, Sun Chan, Roy Dzching Ju, Gueiyuan Lueh, Zhaoqing ZhangAbstract:A hardware managed Register stack, Register Stack Engine (RSE), is implemented in Itanium® architecture to provide a unified and flexible Register structure to software. The compiler allocates each procedure a Register stack frame with its size explicitly specified using an alloc instruction. When the total number of Registers used by the procedures on the call stack exceeds the number of physical Registers, RSE performs automatically Register overflows and fills to ensure that the current procedure has its requested Registers available. The Virtual Register stack frames and RSE alleviate the need of explicit spills by the compiler, but our experimental results indicate that a trade-off exists between using stacked Registers and explicit spills under high Register pressure due to the uneven cost between them. In this work, we introduce the stacked Register quota assignment problem based on the observation that reducing stacked Register usage in some procedures could reduce the total memory access time of spilling Registers, which includes the time caused by the loads/stores due to explicit Register spills and RSE overflows/fills. We propose a new inter-procedural algorithm to solve the problem by allocating stacked Registers across procedures based on a quantitative cost model. The results show that our approach can improve performance significantly for the programs with high RSE overflow cost, e.g. perlbmk and crafty, improved by 14% and 3.7%, respectively.
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ICS - Inter-procedural stacked Register allocation for itanium® like architecture
Proceedings of the 17th annual international conference on Supercomputing - ICS '03, 2003Co-Authors: Liu Yang, Sun Chan, Roy Dzching Ju, Gueiyuan Lueh, Zhaoqing ZhangAbstract:A hardware managed Register stack, Register Stack Engine (RSE), is implemented in Itanium® architecture to provide a unified and flexible Register structure to software. The compiler allocates each procedure a Register stack frame with its size explicitly specified using an alloc instruction. When the total number of Registers used by the procedures on the call stack exceeds the number of physical Registers, RSE performs automatically Register overflows and fills to ensure that the current procedure has its requested Registers available. The Virtual Register stack frames and RSE alleviate the need of explicit spills by the compiler, but our experimental results indicate that a trade-off exists between using stacked Registers and explicit spills under high Register pressure due to the uneven cost between them. In this work, we introduce the stacked Register quota assignment problem based on the observation that reducing stacked Register usage in some procedures could reduce the total memory access time of spilling Registers, which includes the time caused by the loads/stores due to explicit Register spills and RSE overflows/fills. We propose a new inter-procedural algorithm to solve the problem by allocating stacked Registers across procedures based on a quantitative cost model. The results show that our approach can improve performance significantly for the programs with high RSE overflow cost, e.g. perlbmk and crafty, improved by 14% and 3.7%, respectively.
