The Experts below are selected from a list of 15297 Experts worldwide ranked by ideXlab platform
Nasa - One of the best experts on this subject based on the ideXlab platform.
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TOPEX/POSEIDON joint Verification Plan
2019Co-Authors: NasaAbstract:TOPEX/POSEIDON is a satellite mission that will use altimetry to make precise measurements of sea level with the primary goal of studying global ocean circulation. The mission is jointly conducted by the United States' National Aeronautics and Space Administration (NASA) and the French space agency, Centre National d'Etudes Spatiales (CNES). The current Plans call for a launch of the satellite in August 1992. The primary mission will last 3 years, and provisions were made to extend the mission for an additional 2 years. The mission was coordinated with a number of international oceanographic and meteorological programs, including the World Ocean Circulation Experiment and the Tropical Ocean and Global Atmosphere Program, both of which are sponsored by the World Climate Research Program. The observations of TOPEX/POSEIDON are timed to provide a global perspective for interpreting the in situ measurements collected by these programs and in turn will be combined with observations of other satellites to achieve a global, four-dimensional description of the circulation of the world's oceans. In the autumn of 1987, an international team of 38 Principal Investigators was selected to participate in the mission. These scientists have been working closely with the TOPEX/POSEIDON Project to refine the mission design and science Plans. During the first 6 months after launch, a number of these investigators will join with the project to conduct a wide range of oceanographic and geophysical investigations using the TOPEX/POSEIDON data. The purpose of these investigations is to demonstrate the scientific utility of the mission to the international scientific community.
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Preliminary design review package on air flat plate collector for solar heating and cooling system
2013Co-Authors: NasaAbstract:Guidelines to be used in the development and fabrication of a prototype air flat plate collector subsystem containing 320 square feet (10-4 ft x 8 ft panels) of collector area are presented. Topics discussed include: (1) Verification Plan; (2) thermal analysis; (3) safety hazard analysis; (4) drawing list; (5) special handling, installation and maintenance tools; (6) structural analysis; and (7) selected drawings.
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Preliminary design package for programmable controller and hydronic energy package
2013Co-Authors: Nasa, Sunkeeper Control Corp.Abstract:Information necessary to evaluate the preliminary design of the sunkeeper controller is presented as a compilation of the following documents: development Plan, Verification Plan, hazard analysis, drawing list, and other information pertaining to the design of the subsystem.
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Integrated guidance, navigation and control Verification Plan primary flight system
2013Co-Authors: NasaAbstract:The Verification process and requirements for the ascent guidance interfaces and the ascent integrated guidance, navigation and control system for the space shuttle orbiter are defined as well as portions of supporting systems which directly interface with the system. The ascent phase of Verification covers the normal and ATO ascent through the final OMS-2 circularization burn (all of OPS-1), the AOA ascent through the OMS-1 burn, and the RTLS ascent through ET separation (all of MM 601). In addition, OPS translation Verification is defined. Verification trees and roadmaps are given.
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Qualification test and analysis report: Solar collectors
2013Co-Authors: NasaAbstract:Test results show that the Owens-Illinois Sunpak TM Model SEC 601 air-cooled collector meets the national standards and codes as defined in the Subsystem Peformance Specification and Verification Plan of NASA/MSFC, dated October 28, 1976. The program calls for the development, fabrication, qualification and delivery of an air-cooled solar collector for solar heating, combined heating and cooling, and/or hot water systems.
Ashok B. Mehta - One of the best experts on this subject based on the ideXlab platform.
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Functional Verification: Challenges and Solutions
ASIC SoC Functional Design Verification, 2018Co-Authors: Ashok B. MehtaAbstract:This chapter will discuss the overall design Verification (DV) challenges and solutions. Why is DV still such a long pole in the design cycle? We will discuss a comprehensive Verification Plan and see the type of expertise required at each step of Verification and how to improve the develop => simulate => debug => cover loop.
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Voice Over IP (VoIP) Network SoC Verification
ASIC SoC Functional Design Verification, 2018Co-Authors: Ashok B. MehtaAbstract:This chapter discusses, in detail, the Verification of a complex SoC, namely, a voice over IP Network SoC. We will go through a comprehensive Verification Plan and describe each Verification step with VoIP SoC-based real-life detail.
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Cache Memory Subsystem Verification: ISS Based
ASIC SoC Functional Design Verification, 2017Co-Authors: Ashok B. MehtaAbstract:This chapter discusses, in detail, the Verification of a cache subsystem of a larger SoC. We will go through a comprehensive Verification Plan and describe at each Verification step, cache subsystem-based real-life detail. This chapter discusses the Verification methodology using an instruction set simulator (ISS) (as opposed to an UVM agent which is described in Chap. 17).
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Cache Memory Subsystem Verification: UVM Agent Based
ASIC SoC Functional Design Verification, 2017Co-Authors: Ashok B. MehtaAbstract:This chapter discusses, in detail, Verification of a cache subsystem of a large SoC. We will go through a comprehensive Verification Plan and describe, at each Verification step, cache subsystem-based real-life detail. This chapter discusses the Verification methodology using an UVM agent (as opposed to using an instruction set simulator (ISS) which is discussed in the next chapter).
Martin Berglund - One of the best experts on this subject based on the ideXlab platform.
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Shuffled languages—Representation and recognition
Theoretical Computer Science, 2013Co-Authors: Martin Berglund, Henrik Björklund, Johanna BjörklundAbstract:Language models that use interleaving, or shuffle, operators have applications in various areas of computer science, including system Verification, Plan recognition, and natural language processing ...
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The Membership Problem for the Shuffle of Two Deterministic Linear Context-Free Languages is NP-complete
2012Co-Authors: Martin BerglundAbstract:Formal language models which employ shuffling, or interleaving, of strings are of interest in many areas of computer science. Notable examples include system Verification, Plan recognition, and nat ...
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LATA - Recognizing shuffled languages
Language and Automata Theory and Applications, 2011Co-Authors: Martin Berglund, Henrik Björklund, Johanna HögbergAbstract:Language models that use interleaving, or shuffle, operators have applications in various areas of computer science, including system Verification, Plan recognition, and natural language processing. We study the complexity of the membership problem for such models, i.e., how difficult it is to determine if a string belongs to a language or not. In particular, we investigate how interleaving can be introduced into models that capture the context-free languages.
Ken Kundert - One of the best experts on this subject based on the ideXlab platform.
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A Formal Top-Down Design Process for Mixed-Signal Circuits
2006Co-Authors: Ken KundertAbstract:Version 1a, October 2001 With mixed-signal designs becoming more complex and time-to-market windows shrinking, designers cannot hope to keep up unless they change the way they design. They must adopt a more formal process for design and Verification: top-down design. It involves more than simply a cursory design of the circuit block diagram before designing the blocks. Rather, it requires developing and following a formal Verification Plan and an incremental and methodical approach for transforming the design from a abstract block diagram to a detailed transistor-level implementation.
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top down design of mixed signal circuits
2000Co-Authors: Ken KundertAbstract:With mixed-signal designs becoming more complex and time-to-market windows shrinking, designers cannot hope to keep up unless they change the way they design. They must adopt a more formal process for design and Verification: top-down design. It involves more than simply a cursory design of the circuit block diagram before designing the blocks. Rather, it also involves developing and following a formal Verification Plan and an incremental and methodical approach for transforming the design from a abstract block diagram to a detailed transistor-level implementation.
Liang Feng - One of the best experts on this subject based on the ideXlab platform.
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Discussion of reliability Verification Plan for thermal battery
Chinese Journal of Power Sources, 2002Co-Authors: Liang FengAbstract:The reliability Verification Plan for thermal battery was discussed. User can evaluate the reliability of thermal battery by analyzing the accumulating data. Every year, or every 2 or 3 years, or when the total accumulated battery number is more than 500, user can calculate the reliability of the thermal battery by formula (1) and calculate its light and heavy defects by adopting the weight of 0.2 and 0.6 respectively. Manufacturer can evaluate the reliability by analyzing the accumulated data of annual sampling data and calculating the activation and the operating time of the thermal battery in accordance with the standard GJB 376. The evaluation method of the reliability of engineering product of fire. The specially organized reliability Verification experiment is mentioned as follow: define the subsample number as 75, select the activation time and operating time to calculate the exact value of reliability of the thermal battery; calculate the reliability of the thermal battery with stable manufacturing and technical status by formula (15); calculate the reliability of the thermal battery by formula (11) in qualification experiment, that is, calculate the data of thermal battery operated at high, low and ambient temperature respectively and determine it is unqualified if it works unqualified under one of the three conditions.