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Huzur Saran - One of the best experts on this subject based on the ideXlab platform.

  • An empirical evaluation of virtual circuit holding time policies in IP-over-ATM networks
    IEEE Journal on Selected Areas in Communications, 1995
    Co-Authors: Srinivasan Keshav, Carsten Lund, Steven J. Phillips, Nick Reingold, Huzur Saran
    Abstract:

    When carrying Internet protocol (IP) traffic over an asynchronous transfer mode (ATM) network, the ATM adaptation layer must determine how long to hold a virtual circuit opened to carry an IP datagram. We present a formal statement of the problem and carry out a detailed empirical examination of various holding time policies taking into account the issue of network pricing. We offer solutions for two natural pricing models, the first being a likely pricing model of future ATM networks, while the second is based on characteristics of current networks. For each pricing model, we study a variety of simple nonadaptive policies as well as easy to implement policies that adapt to the characteristics of the IP traffic. We simulate our policies on actual network traffic, and find that policies based on least recently used (LRU) perform well, although the best adaptive policies provide a significant improvement over LRU. >

  • an empirical evaluation of virtual circuit holding times in ip over atm networks
    International Conference on Computer Communications, 1994
    Co-Authors: Huzur Saran, Srinivasan Keshav
    Abstract:

    When carrying Internet Protocol (IP) traffic over an asynchronous transfer mode (ATM) network, the ATM adaptation layer must determine how long to hold a virtual circuit opened to carry an IP datagram. The authors present a formal statement of the problem and an empirical study of holding time policies taking network pricing into account. They find that IP traffic shows temporal locality of reference and so least recently used (LRU)-based policies perform well. A system-wide timeout, which is a special case of an LRU policy, is quite effective when the timeout value is chosen correctly. The policies proposed are easy to implement and solve the problem satisfactorily. >

Srinivasan Keshav - One of the best experts on this subject based on the ideXlab platform.

  • An empirical evaluation of virtual circuit holding time policies in IP-over-ATM networks
    IEEE Journal on Selected Areas in Communications, 1995
    Co-Authors: Srinivasan Keshav, Carsten Lund, Steven J. Phillips, Nick Reingold, Huzur Saran
    Abstract:

    When carrying Internet protocol (IP) traffic over an asynchronous transfer mode (ATM) network, the ATM adaptation layer must determine how long to hold a virtual circuit opened to carry an IP datagram. We present a formal statement of the problem and carry out a detailed empirical examination of various holding time policies taking into account the issue of network pricing. We offer solutions for two natural pricing models, the first being a likely pricing model of future ATM networks, while the second is based on characteristics of current networks. For each pricing model, we study a variety of simple nonadaptive policies as well as easy to implement policies that adapt to the characteristics of the IP traffic. We simulate our policies on actual network traffic, and find that policies based on least recently used (LRU) perform well, although the best adaptive policies provide a significant improvement over LRU. >

  • an empirical evaluation of virtual circuit holding times in ip over atm networks
    International Conference on Computer Communications, 1994
    Co-Authors: Huzur Saran, Srinivasan Keshav
    Abstract:

    When carrying Internet Protocol (IP) traffic over an asynchronous transfer mode (ATM) network, the ATM adaptation layer must determine how long to hold a virtual circuit opened to carry an IP datagram. The authors present a formal statement of the problem and an empirical study of holding time policies taking network pricing into account. They find that IP traffic shows temporal locality of reference and so least recently used (LRU)-based policies perform well. A system-wide timeout, which is a special case of an LRU policy, is quite effective when the timeout value is chosen correctly. The policies proposed are easy to implement and solve the problem satisfactorily. >

Axel Jantsch - One of the best experts on this subject based on the ideXlab platform.

  • tdm virtual circuit configuration for network on chip
    IEEE Transactions on Very Large Scale Integration Systems, 2008
    Co-Authors: Axel Jantsch
    Abstract:

    In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns to share buffers and link bandwidth using dedicated time slots. In the paper, we first give a formulation of the multinode VC configuration problem for arbitrary NoC topologies. A multinode VC allows multiple source and destination nodes on it. Then we address the two problems of path selection and slot allocation for TDM VC configuration. For the path selection, we use a backtracking algorithm to explore the path diversity, constructively searching the solution space. In the slot allocation phase, overlapped VCs must be configured such that no conflict occurs and their bandwidth requirements are satisfied. We define the concept of a logical network (LN) as an infinite set of associated (time slot, buffer) pairs with respect to a buffer on a given VC. Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. They are applicable for networks where all nodes operate with the same clock frequency but allowing different phases. Using these theorems, slot allocation for VCs is a procedure of assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. Our experiments on synthetic and real applications validate the effectiveness and efficiency of our approach.

  • slot allocation using logical networks for tdm virtual circuit configuration for network on chip
    International Conference on Computer Aided Design, 2007
    Co-Authors: Axel Jantsch
    Abstract:

    Configuring Time-Division-Multiplexing (TDM) virtual circuits (VCs) for network-on-chip must guarantee conflict freedom for overlapping VCs besides allocating sufficient time slots to them. These requirements are fulfilled in the slot allocation phase. In the paper, we define the concept of a logical network (LN). Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. Using these theorems, slot allocation for VCs becomes a procedure of computing LNs and then assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. We have integrated this slot allocation method into our multi-node VC configuration program and applied the program to an industrial application.

Gyselinck Johan - One of the best experts on this subject based on the ideXlab platform.

  • Active-Damping virtual circuit Control for Grid-Tied Converters with Differential-Mode and Common-Mode Output Filters
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Niyomsatian Korawich, Vanassche Piet, Gyselinck Johan, Sabariego Ruth
    Abstract:

    This paper presents a virtual circuit control (VCC) method of designing a resonant-damping discrete-time controller for grid-tied voltage source converters with differential-mode (DM) and common-mode (CM) output filters. The method provides an intuitive way to specify the desired closed-loop behavior by means of a virtual reference circuit rather than abstract mathematical criteria such as closed-loop poles and weighting matrices. Therefore, the existing passive filter designs, which cannot be practically implemented due to excessive losses, and the well-established theory of filters can be exploited. The DM grid current and the CM capacitor voltage, which are the primary control objectives, inherit the main properties of their underlying virtual reference circuits, e.g. resonance damping and low-frequency behavior. On this account, to fortify the controller against grid impedance variations, a virtual circuit with a series resistor at the grid side is considered. Accordingly, the CM voltage and DM current controllers can be easily designed based on the low-frequency behavior of virtual circuits. The method can also be straightforwardly equipped with conventional controllers to enhance system performance, such as harmonic compensation. The simulation and experimental results verify the effectiveness of the DM and CM resonant damping and dynamic performance.status: Published onlin

  • Active-Damping virtual circuit Control for Grid-Tied Converters with Differential-Mode and Common-Mode Output Filters
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Niyomsatian Korawich, Vanassche Piet, Gyselinck Johan, Sabariego Ruth
    Abstract:

    This article presents a virtual circuit control method of designing a resonant-damping discrete-time controller for grid-tied voltage source converters with differential-mode (DM) and common-mode (CM) output filters. The method provides an intuitive way to specify the desired closed-loop behavior by means of a virtual reference circuit rather than abstract mathematical criteria such as closed-loop poles and weighting matrices. Therefore, the existing passive filter designs, which cannot be practically implemented due to excessive losses, and the well-established theory of filters can be exploited. The DM grid current and the CM capacitor voltage, which are the primary control objectives, inherit the main properties of their underlying virtual reference circuits, e.g. resonance damping and low-frequency behavior. On this account, to fortify the controller against grid impedance variations, a virtual circuit with a series resistor at the grid side is considered. Accordingly, the CM voltage and DM current controllers can be easily designed based on the low-frequency behavior of virtual circuits. The method can also be straightforwardly equipped with conventional controllers to enhance system performance, such as harmonic compensation. The simulation and experimental results verify the effectiveness of the DM and CM resonant damping and dynamic performance.SCOPUS: ar.jinfo:eu-repo/semantics/publishe

  • Systematic control design for half-bridge converters with LCL output filters through virtual circuit similarity transformations
    IEEE, 2017
    Co-Authors: Niyomsatian Korawich, Vanassche Piet, Sabariego Ruth, Gyselinck Johan
    Abstract:

    This paper presents the systematic design and performance of two controls for half-bridge converters with LCL output filters based on a similarity transformation. This type of converters is commonly used in, for example, grid or battery interfaces. Both controls feature active damping, i.e. filter resonances are damped through software and not by using passive resistors. Moreover, both controls are designed using the virtual circuit Design method, which is an intuitive way for designing controls with closed-loop behaviour specified by means of a — virtual — reference circuit through a similarity transformation. The converters controlled through virtual circuit inherit many properties of their underlying reference circuit, including resonance damping, robustness and low-frequency behaviour. The experimental results demonstrate both controls to properly damp resonances. At low frequencies the first design presents itself as a resistor while the second design acts as an inductor. Supervisory current controllers treat the system accordingly.status: publishe

  • Comparison of virtual circuit-based control designs for half-bridge converters with LCL output filters
    'Institute of Electrical and Electronics Engineers (IEEE)', 2017
    Co-Authors: Niyomsatian Korawich, Vanassche Piet, Sabariego Ruth, Gyselinck Johan
    Abstract:

    This paper compares the design and performance of two controls for half-bridge converters with LCL output filters based on virtual circuit Design method, which is an intuitive way to achieve desired closed-loop behaviours as well as resonance damping and low-frequency behaviours. The first control is represented by a circuit employing a resistor in series with a converter-side inductor to stabilize the resonance while the second one by a resistor in parallel with a filter capacitor. This yields different low-frequency behaviours and different designs of the current controllers. Moreover, both circuits feature the adjustable virtual inductance to improve the bandwidth and the robustness. The experiment illustrates excellent performances from the step response and fair robustness against grid-inductance variation.info:eu-repo/semantics/publishe

Andrzej Bartoszewicz - One of the best experts on this subject based on the ideXlab platform.

  • 5ROBUST FLOW CONTROLLERS FOR A SINGLE virtual circuit IN DATA TRANSMISSION NETWORKS WITH LOSSY LINKS
    2016
    Co-Authors: Andrzej Bartoszewicz, Piotr Leśniewski
    Abstract:

    The paper concerns an application of regulation theory methods to modeling and effective control of connection-oriented data transmission networks. In particular the problem of congestion control in a single virtual circuit of such a network is considered and new discrete-time sliding mode data flow rate controllers are proposed. The controllers are designed in such a way that packet losses are explicitly accounted for. The closed-loop system stability and finite-time error convergence are proved. Moreover, a number of favorable properties of the proposed controllers are stated as theorems, formally proved and verified in a simulation example. It is demonstrated that the proposed controllers guarantee full utilization of the available bandwidth and eliminates the risk of bottleneck node buffer overflow. Application of time-varying sliding hyperplanes helps avoid excessive transmission rates at the beginning of the control process. Key words: data transmission networks, congestion control, sliding-mode control, discrete-time systems

  • Robust Congestion Controller for a Single virtual circuit in Connection-Oriented Communication Networks
    Variable-Structure Approaches, 2016
    Co-Authors: Piotr Leśniewski, Andrzej Bartoszewicz
    Abstract:

    In this contribution, we consider the problem of data flow control for a single virtual connection in communication networks. The connection is described by the maximum link capacity, the non-negligible propagation delay and an unknown, time-varying data loss rate. We propose a discrete-time sliding mode controller, which generates non-negative and upper bounded transmission rates. In addition, it ensures that the queue length in the bottleneck link buffer is always limited. Moreover, with a sufficiently large memory buffer in the bottleneck node, it guarantees full utilization of the available bandwidth. The controller uses a dead-beat sliding hyperplane in order to ensure fast response to unknown changes of the link capacity and to an unpredictable data loss rate. However, if the straightforward dead-beat paradigm was used, unacceptably large transmission rates would be generated. Therefore, we use the reaching law approach in this chapter to decrease excessive magnitudes of the control signal at the start of the control process.

  • sliding mode data flow regulation for connection oriented networks with unpredictable packet loss ratio
    European Consortium for Mathematics in Industry, 2014
    Co-Authors: Piotr Lesniewski, Andrzej Bartoszewicz
    Abstract:

    In this paper we propose a discrete time sliding mode congestion controller for a single virtual circuit in connection-oriented communication networks. The circuit is characterized by the non-negligible propagation delay, the maximum link capacity and unknown, time-varying data loss rate. The proposed controller generates non-negative and limited transmission rates, ensures upper bounded queue length in the bottleneck link buffer and may guarantee full utilization of the link capacity. In order to ensure fast reaction to the unpredictable data loss and unknown changes of the available bandwidth, the controller employs the dead-beat sliding hyperplane. However, straightforward application of the dead-beat paradigm could lead to unacceptably big transmission rates. Therefore, the controller is designed using the concept of the reaching law, which helps to attenuate the excessive magnitude of control signal at the beginning of the transmission process.

  • robust flow controller for a single virtual circuit in connection oriented networks with lossy links
    International Conference on Methods and Models in Automation and Robotics, 2012
    Co-Authors: Andrzej Bartoszewicz, Piotr Lesniewski
    Abstract:

    In this paper we propose a discrete-time sliding mode flow controller for a single virtual circuit in connection-oriented communication networks. The controller is designed to be robust with respect to unknown packet losses, provided that they are in a known range. The closed-loop system stability is proved. Furthermore, the proposed controller ensures no bottleneck node buffer overflow and full consumption of the available bandwidth.

  • sliding mode congestion control for a single virtual circuit in connection oriented networks with lossy links
    International Carpathian Control Conference, 2012
    Co-Authors: Andrzej Bartoszewicz, Piotr Lesniewski
    Abstract:

    This paper presents a new discrete-time sliding mode flow controller for a single virtual circuit in connection-oriented communication networks. The controller is designed in such a way that packet losses are explicitly taken into account. The closed-loop system stability and finite-time error convergence are proved. Moreover, the proposed controller guarantees no bottleneck node buffer overflow and full utilization of the available bandwidth. Application of time-varying sliding hyperplanes helps avoid excessive transmission rates at the beginning of the control process.