The Experts below are selected from a list of 213 Experts worldwide ranked by ideXlab platform
Youliang Yan - One of the best experts on this subject based on the ideXlab platform.
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rhymes a shared Virtual Memory System for non coherent tiled many core architectures
International Conference on Parallel and Distributed Systems, 2014Co-Authors: King Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
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ICPADS - Rhymes: A shared Virtual Memory System for non-coherent tiled many-core architectures
2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS), 2014Co-Authors: Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
King Tin Lam - One of the best experts on this subject based on the ideXlab platform.
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rhymes a shared Virtual Memory System for non coherent tiled many core architectures
International Conference on Parallel and Distributed Systems, 2014Co-Authors: King Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
L. Bela - One of the best experts on this subject based on the ideXlab platform.
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RTSS - A Virtual Memory System for real-time applications
[1992] Proceedings Real-Time Systems Symposium, 1Co-Authors: C.c. Bakshi, L. BelaAbstract:A Virtual Memory implementation for a real-time environment is presented. The authors considered the special needs of real-time clients and provided a programmable mechanism for clients to control their Memory resource needs and constraints. As a design goal they wanted the API to be as simple as possible. They made it look similar to the Unix interface so that client programs could be ported easily from Unix to the target environment. The authors viewed the implementation as risky from the onset and as a result planned on various mechanisms to tune the System. They also planned on extensive performance tools for the same reason. They have seen benefits in the potential flexibility due to this implementation. The authors describe the client interface, implementation details, performance results from the initial implementation, and recent efficiency improvements. >
Zhiquan Lai - One of the best experts on this subject based on the ideXlab platform.
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rhymes a shared Virtual Memory System for non coherent tiled many core architectures
International Conference on Parallel and Distributed Systems, 2014Co-Authors: King Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
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ICPADS - Rhymes: A shared Virtual Memory System for non-coherent tiled many-core architectures
2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS), 2014Co-Authors: Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
Jinghao Shi - One of the best experts on this subject based on the ideXlab platform.
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rhymes a shared Virtual Memory System for non coherent tiled many core architectures
International Conference on Parallel and Distributed Systems, 2014Co-Authors: King Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
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ICPADS - Rhymes: A shared Virtual Memory System for non-coherent tiled many-core architectures
2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS), 2014Co-Authors: Tin Lam, Jinghao Shi, Dominic Hung, Choli Wang, Zhiquan Lai, Wangbin Zhu, Youliang YanAbstract:The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified by the Intel Single-chip Cloud Computer (SCC), promotes a software-oriented approach instead of hardware support to implementing shared Memory coherence. This paper presents a shared Virtual Memory (SVM) System, dubbed Rhymes, tailored to new processor kinds of non-coherent and hybrid Memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical Memory (SPM) and scope consistency for pages in percore private Memory. It also supports page remapping on a percore basis to boost data locality. We implement and test Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times through improved cache utilization for applications with strong data reuse patterns.
