The Experts below are selected from a list of 234 Experts worldwide ranked by ideXlab platform
Trishul Chilimbi - One of the best experts on this subject based on the ideXlab platform.
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Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management
2016Co-Authors: Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing memory at a Vne (e.g., cache line) granularity—e.g., Vne-grained deduplication and Vne-grained memory protection. Unfortunately, existing vir-tual memory systems track memory at a larger granularity (e.g., 4 KB Pages), inhibiting eXcient implementation of such techniques. Simply reducing the Page size results in an unac-ceptable increase in Page table overhead and TLB pressure. We propose a new Virtual memory framework that enables eXcient implementation of a variety of Vne-grained memory management techniques. In our framework, each Virtual Page can be mapped to a structure called a Page overlay, in addi-tion to a regular physical Page. An overlay contains a subset of cache lines from the Virtual Page. Cache lines that are presen
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ISCA - Page overlays: an enhanced Virtual memory framework to enable fine-grained memory management
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing memory at a fine (e.g., cache line) granularity---e.g., fine-grained deduplication and fine-grained memory protection. Unfortunately, existing Virtual memory systems track memory at a larger granularity (e.g., 4 KB Pages), inhibiting efficient implementation of such techniques. Simply reducing the Page size results in an unacceptable increase in Page table overhead and TLB pressure. We propose a new Virtual memory framework that enables efficient implementation of a variety of fine-grained memory management techniques. In our framework, each Virtual Page can be mapped to a structure called a Page overlay, in addition to a regular physical Page. An overlay contains a subset of cache lines from the Virtual Page. Cache lines that are present in the overlay are accessed from there and all other cache lines are accessed from the regular physical Page. Our Page-overlay framework enables cache-line-granularity memory management without significantly altering the existing Virtual memory framework or introducing high overheads. We show that our framework can enable simple and efficient implementations of seven memory management techniques, each of which has a wide variety of applications. We quantitatively evaluate the potential benefits of two of these techniques: overlay-on-write and sparse-data-structure computation. Our evaluations show that overlay-on-write, when applied to fork, can improve performance by 15% and reduce memory capacity requirements by 53% on average compared to traditional copy-on-write. For sparse data computation, our framework can outperform a state-of-the-art software-based sparse representation on a number of real-world sparse matrices. Our framework is general, powerful, and effective in enabling fine-grained memory management at low cost.
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Page overlays an enhanced Virtual memory framework to enable fine grained memory management
International Symposium on Computer Architecture, 2015Co-Authors: Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing memory at a fine (e.g., cache line) granularity---e.g., fine-grained deduplication and fine-grained memory protection. Unfortunately, existing Virtual memory systems track memory at a larger granularity (e.g., 4 KB Pages), inhibiting efficient implementation of such techniques. Simply reducing the Page size results in an unacceptable increase in Page table overhead and TLB pressure. We propose a new Virtual memory framework that enables efficient implementation of a variety of fine-grained memory management techniques. In our framework, each Virtual Page can be mapped to a structure called a Page overlay, in addition to a regular physical Page. An overlay contains a subset of cache lines from the Virtual Page. Cache lines that are present in the overlay are accessed from there and all other cache lines are accessed from the regular physical Page. Our Page-overlay framework enables cache-line-granularity memory management without significantly altering the existing Virtual memory framework or introducing high overheads. We show that our framework can enable simple and efficient implementations of seven memory management techniques, each of which has a wide variety of applications. We quantitatively evaluate the potential benefits of two of these techniques: overlay-on-write and sparse-data-structure computation. Our evaluations show that overlay-on-write, when applied to fork, can improve performance by 15% and reduce memory capacity requirements by 53% on average compared to traditional copy-on-write. For sparse data computation, our framework can outperform a state-of-the-art software-based sparse representation on a number of real-world sparse matrices. Our framework is general, powerful, and effective in enabling fine-grained memory management at low cost.
Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.
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A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system
IEEE Journal of Solid-State Circuits, 2001Co-Authors: Yong-ha Park, Seon Ho Han, Jung-hwan Lee, Hoi-jun YooAbstract:A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, Virtual Page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm2 prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge
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7.1 GB/sec bandwidth 3D rendering engine using the EML technology
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1Co-Authors: Yong-ha Park, Ramchan Woo, Se-joong Lee, Sun-ho Han, Jung-su Kim, Jeong-hun Kook, Jae-woon Lim, Hoi-jun YooAbstract:We implement a rendering engine which has 7.1 GB/s bandwidth and 11.1 Mpolygon/s drawing speed. It has 3D rendering functions such as double buffering, smooth shading, alpha blending and depth comparison. It can convert 3D primitives into complete pixel data in every 90 ns. A serial access memory permits simultaneous memory access both for rendering operation and for screen refresh operation. The proposed Virtual Page mapping performs rendering operation without a Page miss irrespective of the location of a polygon in the screen. Also, the partial word line activation and the sequential block activation can reduce the power consumption of 64 concurrent memory arrays to only 1.2 W.
Vivek Seshadri - One of the best experts on this subject based on the ideXlab platform.
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Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management
2016Co-Authors: Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing memory at a Vne (e.g., cache line) granularity—e.g., Vne-grained deduplication and Vne-grained memory protection. Unfortunately, existing vir-tual memory systems track memory at a larger granularity (e.g., 4 KB Pages), inhibiting eXcient implementation of such techniques. Simply reducing the Page size results in an unac-ceptable increase in Page table overhead and TLB pressure. We propose a new Virtual memory framework that enables eXcient implementation of a variety of Vne-grained memory management techniques. In our framework, each Virtual Page can be mapped to a structure called a Page overlay, in addi-tion to a regular physical Page. An overlay contains a subset of cache lines from the Virtual Page. Cache lines that are presen
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ISCA - Page overlays: an enhanced Virtual memory framework to enable fine-grained memory management
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing memory at a fine (e.g., cache line) granularity---e.g., fine-grained deduplication and fine-grained memory protection. Unfortunately, existing Virtual memory systems track memory at a larger granularity (e.g., 4 KB Pages), inhibiting efficient implementation of such techniques. Simply reducing the Page size results in an unacceptable increase in Page table overhead and TLB pressure. We propose a new Virtual memory framework that enables efficient implementation of a variety of fine-grained memory management techniques. In our framework, each Virtual Page can be mapped to a structure called a Page overlay, in addition to a regular physical Page. An overlay contains a subset of cache lines from the Virtual Page. Cache lines that are present in the overlay are accessed from there and all other cache lines are accessed from the regular physical Page. Our Page-overlay framework enables cache-line-granularity memory management without significantly altering the existing Virtual memory framework or introducing high overheads. We show that our framework can enable simple and efficient implementations of seven memory management techniques, each of which has a wide variety of applications. We quantitatively evaluate the potential benefits of two of these techniques: overlay-on-write and sparse-data-structure computation. Our evaluations show that overlay-on-write, when applied to fork, can improve performance by 15% and reduce memory capacity requirements by 53% on average compared to traditional copy-on-write. For sparse data computation, our framework can outperform a state-of-the-art software-based sparse representation on a number of real-world sparse matrices. Our framework is general, powerful, and effective in enabling fine-grained memory management at low cost.
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Page overlays an enhanced Virtual memory framework to enable fine grained memory management
International Symposium on Computer Architecture, 2015Co-Authors: Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul ChilimbiAbstract:Many recent works propose mechanisms demonstrating the potential advantages of managing memory at a fine (e.g., cache line) granularity---e.g., fine-grained deduplication and fine-grained memory protection. Unfortunately, existing Virtual memory systems track memory at a larger granularity (e.g., 4 KB Pages), inhibiting efficient implementation of such techniques. Simply reducing the Page size results in an unacceptable increase in Page table overhead and TLB pressure. We propose a new Virtual memory framework that enables efficient implementation of a variety of fine-grained memory management techniques. In our framework, each Virtual Page can be mapped to a structure called a Page overlay, in addition to a regular physical Page. An overlay contains a subset of cache lines from the Virtual Page. Cache lines that are present in the overlay are accessed from there and all other cache lines are accessed from the regular physical Page. Our Page-overlay framework enables cache-line-granularity memory management without significantly altering the existing Virtual memory framework or introducing high overheads. We show that our framework can enable simple and efficient implementations of seven memory management techniques, each of which has a wide variety of applications. We quantitatively evaluate the potential benefits of two of these techniques: overlay-on-write and sparse-data-structure computation. Our evaluations show that overlay-on-write, when applied to fork, can improve performance by 15% and reduce memory capacity requirements by 53% on average compared to traditional copy-on-write. For sparse data computation, our framework can outperform a state-of-the-art software-based sparse representation on a number of real-world sparse matrices. Our framework is general, powerful, and effective in enabling fine-grained memory management at low cost.
Chong Sang Kim - One of the best experts on this subject based on the ideXlab platform.
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U-cache: A cost-effective solution to the Virtual cache synonym problem
Microprocessors and Microsystems, 1998Co-Authors: Jesung Kim, Sang Lyul Min, Chong Sang KimAbstract:Abstract This paper proposes a cost-effective solution to the Virtual cache synonym problem. In the proposed solution, a minimal hardware addition guarantees correct handling of the synonym problem whereas a simple modification to the Virtual-to-physical address mapping in the operating system optimizes the performance. The key to the proposed solution is a small, physically-indexed cache called a U-cache. The U-cache maintains the reverse translation information of cache blocks that belong to unaligned Virtual Pages, where unaligned means that the lower bits of the Virtual Page number that are used to index the Virtual cache do not match those of the corresponding physical Page number. The biggest advantage of the U-cache approach is that it leaves room for software optimization in the form of mapping alignment. Performance evaluation based on memory reference traces from a real system shows that the U-cache, with only a few entries, performs almost as well as (in some cases outperforms) a fully-configured hardware-based solution when more than 95% of mappings are aligned.
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HPCA - U-cache: a cost-effective solution to synonym problem
Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture, 1Co-Authors: Jesung Kim, Sang Lyul Min, Sanghoon Jeon, Byoungchu Ahn, Deog-kyoon Jeong, Chong Sang KimAbstract:This paper proposes a cost-effective solution to the synonym problem. In this proposed solution, a minimal hardware addition guarantees the correctness whereas the software counterpart helps improve the performance. The key to this proposed solution is an addition of a small physically-indexed cache called U-cache. The U-cache maintains the reverse translation information of the cache blocks that belong to un-aligned Virtual Pages only, where aligned means that the lower bits of the Virtual Page number match those of the corresponding physical Page number. A U-cache, even with only one entry, ensures correct handling of synonyms. A simple software optimization in the form of Page alignment, helps improve the performance. Performance evaluation based on ATUM traces shows that a U-cache, with only a few entries, performs almost as well as (in some cases outperforms) a fully-configured hardware-based solution when more than 95% of the Pages are aligned. >
Drago Zagar - One of the best experts on this subject based on the ideXlab platform.
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javascript Virtual web Page for wireless sensor node under avr microcontroller architecture
Joint IFIP Wireless and Mobile Networking Conference, 2010Co-Authors: Damir Sostaric, Davor Vinko, Drago ZagarAbstract:This paper presents a developed wireless sensor node with an embedded JavaScript Virtual web Page implemented in the AVR microcontroller architecture. The presented design is capable of operating in real-time environment and has an improved performance with respect to the previously developed HTML Virtual Page. The major advantage of the presented system over the existing ones is the fact that the remote monitoring and control system is fully integrated in the microcontroller. The microcontroller is accessible over the Ethernet and with an integrated Virtual web Page it can replace the web server commonly used in similar systems. This feature makes the presented design extremely cost effective.
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WMNC - JavaScript Virtual web Page for wireless sensor node under AVR microcontroller architecture
WMNC2010, 2010Co-Authors: Damir Šoštarić, Davor Vinko, Drago ZagarAbstract:This paper presents a developed wireless sensor node with an embedded JavaScript Virtual web Page implemented in the AVR microcontroller architecture. The presented design is capable of operating in real-time environment and has an improved performance with respect to the previously developed HTML Virtual Page. The major advantage of the presented system over the existing ones is the fact that the remote monitoring and control system is fully integrated in the microcontroller. The microcontroller is accessible over the Ethernet and with an integrated Virtual web Page it can replace the web server commonly used in similar systems. This feature makes the presented design extremely cost effective.
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Monitoring and Administration of Peripheral Devices Using Wireless Sensor Node
2010Co-Authors: Damir Šoštarić, Krešimir Grgić, Drago ZagarAbstract:This paper describes the implementation of IEEE 802.3 and IEEE 802.11 standards into wireless sensor node (WSN1). Such a WSN1 is intended for applications in everyday life. Physical model describes the architecture of microcontroller and Ethernet chip. Sampling time depends the working hours of the WSN. It is implemented in firmware from user which causes central power unit relieved. Connected peripheral devices may be sensors or actuators that control the analogue or digital environment. Through the Virtual Page generated from HTML code it is possible to control and monitor measurement value. WSN applications are compared with existing platforms. A possibility of an upgrade exists, towards greater number of analog/digital inputs or digital outputs.
