The Experts below are selected from a list of 5178 Experts worldwide ranked by ideXlab platform
Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.
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Development of a 3-D graphics Rendering Engine with lighting acceleration for handheld multimedia systems
IEEE Transactions on Consumer Electronics, 2005Co-Authors: Byeong-gyu Nam, Min-wuk Lee, Hoi-jun YooAbstract:Low-power three-dimensional (3-D) graphics Rendering Engine with lighting acceleration is designed and implemented for handheld multimedia terminals. The lighting unit is hardware implemented and integrated into the chip for the low-power acceleration of the 3D graphics applications. We adopt the following three steps to handle the memory bandwidth problem for Rendering operations. I) We find bilinear MIPMAP is the best texture filtering algorithm for handheld systems based on our developed energy-efficiency metric. With this observation, we adopt bilinear MIPMAP for our texture filtering unit, which requires only 50% of texture memory bandwidth compared with trilinear MIPMAP filtering. II) We put the depth test operation into the earlier stage of the graphics pipeline, which eliminates texture memory accesses for invisible pixels. III) We develop a power-efficient small cache system as the interface to Rendering memory. The accelerator takes 181 K gates and the performance reaches 20 Mpixels/s. A test chip is implemented with 1-poly 6-metal 0.18 /spl mu/m CMOS technology. It operates at the frequency of 20 MHz with 14.7 mW power consumption.
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A low-power 3D Rendering Engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals
IEEE Journal of Solid-State Circuits, 2004Co-Authors: Ramchan Woo, Sungdae Choi, Ju-ho Sohn, Seong-jun Song, Young-don Bae, Hoi-jun YooAbstract:A low-power three-dimensional (3-D) Rendering Engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-/spl mu/m pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm/sup 2/ and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board.
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A 120-mW 3-D Rendering Engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip
IEEE Journal of Solid-State Circuits, 2002Co-Authors: Ramchan Woo, Chi-weon Yoon, Jeonghoon Kook, Se-joong Lee, Hoi-jun YooAbstract:A low-power three-dimensional (3-D) Rendering Engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel Rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D Rendering Engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-/spl mu/m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW.
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a 120 mw embedded 3d graphics Rendering Engine with 6 mb logically local frame buffer and 3 2 gbyte s run time reconfigurable bus for pda chip
Symposium on VLSI Circuits, 2001Co-Authors: Ramchan Woo, Chi-weon Yoon, Jeonghoon Kook, Se-joong Lee, Kangmin Lee, Yong-ha Park, Hoi-jun YooAbstract:An embedded 3D graphics Rendering Engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel Rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.
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single chip 3d Rendering Engine integrating embedded dram frame buffer and hierarchical octet tree hot array processor with bandwidth amplification
Asia and South Pacific Design Automation Conference, 2001Co-Authors: Yong-ha Park, Seon Ho Han, Hoi-jun YooAbstract:A single chip Rendering Engine that consists of a DRAM frame buffer, an SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56 mm/sup 2/ prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35 /spl mu/m CMOS Embedded Memory Logic (EML) technology.
Yong-ha Park - One of the best experts on this subject based on the ideXlab platform.
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a 120 mw embedded 3d graphics Rendering Engine with 6 mb logically local frame buffer and 3 2 gbyte s run time reconfigurable bus for pda chip
Symposium on VLSI Circuits, 2001Co-Authors: Ramchan Woo, Chi-weon Yoon, Jeonghoon Kook, Se-joong Lee, Kangmin Lee, Yong-ha Park, Hoi-jun YooAbstract:An embedded 3D graphics Rendering Engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel Rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.
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single chip 3d Rendering Engine integrating embedded dram frame buffer and hierarchical octet tree hot array processor with bandwidth amplification
Asia and South Pacific Design Automation Conference, 2001Co-Authors: Yong-ha Park, Seon Ho Han, Hoi-jun YooAbstract:A single chip Rendering Engine that consists of a DRAM frame buffer, an SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56 mm/sup 2/ prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35 /spl mu/m CMOS Embedded Memory Logic (EML) technology.
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A 7.1-GB/s low-power Rendering Engine in 2-D array-embedded memory logic CMOS for portable multimedia system
IEEE Journal of Solid-State Circuits, 2001Co-Authors: Yong-ha Park, Seon Ho Han, Jung-hwan Lee, Hoi-jun YooAbstract:A single-chip Rendering Engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm2 prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge
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A 120 mW embedded 3D graphics Rendering Engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip
VLSI Circuits 2001. Digest of Technical Papers. 2001 Symposium on, 2001Co-Authors: Ramchan Woo, Chi-weon Yoon, Jeonghoon Kook, Se-joong Lee, Kangmin Lee, Yong-ha Park, Hoi-jun YooAbstract:An embedded 3D graphics Rendering Engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel Rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.
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ASP-DAC - Single chip 3D Rendering Engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001Co-Authors: Yong-ha Park, Seon Ho Han, Hoi-jun YooAbstract:A single chip Rendering Engine that consists of a DRAM frame buffer, an SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56 mm/sup 2/ prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35 /spl mu/m CMOS Embedded Memory Logic (EML) technology.
Lee-sup Kim - One of the best experts on this subject based on the ideXlab platform.
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A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine
IEEE Journal of Solid-State Circuits, 2008Co-Authors: Seok-hoon Kim, Jaesung Yoon, Kyusik Chung, Hyunwook Park, Donghyun Kim, Han Shin Lim, Yun-gu Lee, Lee-sup KimAbstract:In this paper, a 3D display processor embedding a programmable 3D graphics Rendering Engine is proposed. The proposed processor combines a 3D graphics Rendering Engine and a 3D image synthesis Engine to support both true realism and interactivity for the future multimedia applications. Using high coherence between 3D graphics data and 3D display inputs, both pipelines are merged by sharing buffers such that a 3D display Engine directly uses the output of a 3D graphics Rendering Engine. The merged architecture has synergetic coupling effects such as freely providing various Rendering effects to 3D images and easily computing disparities without complex extraction processes. In the 3D image synthesis Engine, we adopt view interpolation algorithm and propose real-time synthesis method, pixel-by-pixel process. The view interpolation algorithm reduces the number of images to be rendered, resulting in the reduction of external memory size to 64.8% compared to conventional synthesis process. The proposed pixel-by-pixel process synthesizes 3D images at 36 fps through bandwidth reduction of 26.7% and decreases internal memory size to 64.2% compared to typical image-by-image process. The 3D graphics Rendering Engine is programmable and supports the instruction sets of the latest 3D graphics standard APIs, Pixel Shader 3.0 and OpenGL|ES 2.0. The die contains about 1.7 M transistors, occupies 5 mm times 5 mm in 0.18 mum CMOS and dissipates 379 mW at 1.85 V.
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ISSCC - A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007Co-Authors: Seok-hoon Kim, Jaesung Yoon, Kyusik Chung, Hyunwook Park, Donghyun Kim, Han Shin Lim, Lee-sup KimAbstract:A 3D display processor with a programmable 3D graphics Rendering Engine is implemented. The integrated Rendering Engine supports Pixel Shader 3.0 and OpenGL ES 2.0. A 3D image synthesis Engine generates 3D images at 36fps. The die contains 1.74M gates and occupies 5times5mm2 in 0.18mum CMOS and dissipates 379mW at 1.8V.
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ISCAS (2) - An adaptive spatial filter for early depth test
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: Lee-sup KimAbstract:In this paper, we extend our previous work which is a new method for early depth test in a 3D Rendering Engine. We add a filter stage to the rasterizer in the 3D Rendering Engine, in an attempt to identify and avoid the occluded pixels. This filtering block determines if a pixel is hidden by a certain plane. The plane is a mask having the history of a pixel's appearances in front of it. If a pixel is hidden by the plane, it can be removed. The filter adaptively updates its position from an initial position in order to find a maximum rejection ratio. The simulation results show that the filter reduces the number of pixels to the next stage up to 71.7%. As a result, 67% of memory bandwidth is saved with simple extra hardware in the 3D Rendering Engine.
Alex Perelman - One of the best experts on this subject based on the ideXlab platform.
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extensions for 3d graphics Rendering Engine used for direct tessellation of spline surfaces
International Conference on Computational Science, 2006Co-Authors: Adrian Sfarti, Brian A Barsky, Todd J Kosloff, Egon Pasztor, Alex Kozlowski, Eric Roman, Alex PerelmanAbstract:In current 3D graphics architectures, the bus between the triangle server and the Rendering Engine GPU is clogged with triangle vertices and their many attributes (normal vectors, colors, texture coordinates). We have developed a new 3D graphics architecture using data compression to unclog the bus between the triangle server and the Rendering Engine. This new architecture has been described in [1]. In the present paper we describe further developments of the newly proposed architecture. The current paper shows several interesting extensions of our architecture such as backsurface rejection, NURBS real time tesselation and a description of a surface based API. We also show how the implementation of our architecture operates on top of the pixel shaders.
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International Conference on Computational Science (2) - Extensions for 3d graphics Rendering Engine used for direct tessellation of spline surfaces
Computational Science – ICCS 2006, 2006Co-Authors: Adrian Sfarti, Brian A Barsky, Todd J Kosloff, Egon Pasztor, Alex Kozlowski, Eric Roman, Alex PerelmanAbstract:In current 3D graphics architectures, the bus between the triangle server and the Rendering Engine GPU is clogged with triangle vertices and their many attributes (normal vectors, colors, texture coordinates). We have developed a new 3D graphics architecture using data compression to unclog the bus between the triangle server and the Rendering Engine. This new architecture has been described in [1]. In the present paper we describe further developments of the newly proposed architecture. The current paper shows several interesting extensions of our architecture such as backsurface rejection, NURBS real time tesselation and a description of a surface based API. We also show how the implementation of our architecture operates on top of the pixel shaders.
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new 3d graphics Rendering Engine architecture for direct tessellation of spline surfaces
International Conference on Computational Science, 2005Co-Authors: Adrian Sfarti, Brian A Barsky, Todd J Kosloff, Egon Pasztor, Alex Kozlowski, Eric Roman, Alex PerelmanAbstract:In current 3D graphics architectures, the bus between the triangle server and the Rendering Engine GPU is clogged with triangle vertices and their many attributes (normal vectors, colors, texture coordinates). We develop a new 3D graphics architecture using data compression to unclog the bus between the triangle server and the Rendering Engine. The data compression is achieved by replacing the conventional idea of a GPU that renders triangles with a GPU that tessellates surface patches into triangles.
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International Conference on Computational Science (2) - New 3d graphics Rendering Engine architecture for direct tessellation of spline surfaces
Lecture Notes in Computer Science, 2005Co-Authors: Adrian Sfarti, Brian A Barsky, Todd J Kosloff, Egon Pasztor, Alex Kozlowski, Eric Roman, Alex PerelmanAbstract:In current 3D graphics architectures, the bus between the triangle server and the Rendering Engine GPU is clogged with triangle vertices and their many attributes (normal vectors, colors, texture coordinates). We develop a new 3D graphics architecture using data compression to unclog the bus between the triangle server and the Rendering Engine. The data compression is achieved by replacing the conventional idea of a GPU that renders triangles with a GPU that tessellates surface patches into triangles.
Chang-hyo Yu - One of the best experts on this subject based on the ideXlab platform.
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a 36fps sxga 3d display processor with a programmable 3d graphics Rendering Engine
International Solid-State Circuits Conference, 2007Co-Authors: Jaesung Yoon, Chang-hyo Yu, Kyusik Chung, Hyunwook ParkAbstract:A 3D display processor with a programmable 3D graphics Rendering Engine is implemented. The integrated Rendering Engine supports Pixel Shader 3.0 and OpenGL ES 2.0. A 3D image synthesis Engine generates 3D images at 36fps. The die contains 1.74M gates and occupies 5times5mm2 in 0.18mum CMOS and dissipates 379mW at 1.8V.
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an adaptive spatial filter for early depth test
International Symposium on Circuits and Systems, 2004Co-Authors: Chang-hyo YuAbstract:In this paper, we extend our previous work which is a new method for early depth test in a 3D Rendering Engine. We add a filter stage to the rasterizer in the 3D Rendering Engine, in an attempt to identify and avoid the occluded pixels. This filtering block determines if a pixel is hidden by a certain plane. The plane is a mask having the history of a pixel's appearances in front of it. If a pixel is hidden by the plane, it can be removed. The filter adaptively updates its position from an initial position in order to find a maximum rejection ratio. The simulation results show that the filter reduces the number of pixels to the next stage up to 71.7%. As a result, 67% of memory bandwidth is saved with simple extra hardware in the 3D Rendering Engine.
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A hierarchical depth buffer for minimizing memory bandwidth in 3D Rendering Engine: Depth Filter
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 2003Co-Authors: Chang-hyo YuAbstract:In this paper, we propose a new class of hierarchical depth test which saves memory bandwidth in 3D graphics Rendering Engine by reducing the number of pixels being passed to the per-pixel operation pipeline. This new filtering, Depth Filter, can be implemented by adding a simple hardware in front of the per-pixel operation pipeline. The Depth Filter is a filtering block which decides whether a pixel is shaded by certain plane. The plane is the mask which has the history that a pixel has appeared in front of the plane. If the pixel is shaded, the pixel can be removed. The simulation shows that Depth Filter reduces the number of pixels to the next stage up to 62.1 percent in random scene. As a result, 62.1% of memory bandwidth is saved with simple extra hardware.
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ISCAS (2) - A hierarchical depth buffer for minimizing memory bandwidth in 3D Rendering Engine: Depth Filter
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 2003Co-Authors: Chang-hyo YuAbstract:In this paper, we propose a new class of hierarchical depth test which saves memory bandwidth in 3D graphics Rendering Engine by reducing the number of pixels being passed to the per-pixel operation pipeline. This new filtering, Depth Filter, can be implemented by adding a simple hardware in front of the per-pixel operation pipeline. The Depth Filter is a filtering block which decides whether a pixel is shaded by certain plane. The plane is the mask which has the history that a pixel has appeared in front of the plane. If the pixel is shaded, the pixel can be removed. The simulation shows that Depth Filter reduces the number of pixels to the next stage up to 62.1 percent in random scene. As a result, 62.1% of memory bandwidth is saved with simple extra hardware.
