The Experts below are selected from a list of 10185 Experts worldwide ranked by ideXlab platform
Steffen Michael - One of the best experts on this subject based on the ideXlab platform.
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A Hardware-Software Integrated Solution for Improved Single-Instruction Multi-Thread Processor Efficiency
Iowa State University Digital Repository, 2012Co-Authors: Steffen MichaelAbstract:This thesis proposes using an integrated hardware-software solution for improving Single-Instruction Multiple-Thread branching efficiency. Unlike current SIMT hardware branching architectures, this hardware-software solution allows programmers the ability to fine tune branching behavior for their application or allow the compiler to implement a generic software solution. To support a wide range of SIMT applications with different control flow properties, three branching methods are implemented in hardware with configurable software instructions. The three branching methods are the contemporary Immediate Post-Dominator Re-convergence that is currently implemented in SIMT Processors, a proposed Hyper-threaded SIMT Processor for maintaining statically allocated thread warps and a proposed Dynamic Micro-Kernels that modified thread warps during run-time execution. Each of the implemented branching methods have their strengths and weaknesses and result in different performance improvements depending on the application. SIMT hyper-threading turns a single SIMT Processor core into multiple Virtual Processors. These Virtual Processors run divergent control flow paths in parallel with threads from the same warp. Controlling how the Virtual Processor cores are created is done using a per-warp stack that is managed through software instructions. Dynamic Micro-Kernels create new threads at run-time to execute divergent control flow paths instead of using branching instructions. A spawn instruction is used to create threads at run-time and once created are placed into new warps with similar threads following the same control flow path. This thesis\u27s integrated hardware-software branching architectures are evaluated using multiple realistic benchmarks with varying control flow divergence. Synthetic benchmarks are also used for evaluation and are designed to test specific branching conditions and isolate common branching behaviors. Each of the hardware implemented branching solutions are tested in isolation using different software algorithms. Results show improved performance for divergent applications and using different software algorithms will affect performance
Michael Steffen - One of the best experts on this subject based on the ideXlab platform.
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a hardware software integrated solution for improved single instruction multi thread Processor efficiency
2012Co-Authors: Michael SteffenAbstract:This thesis proposes using an integrated hardware-software solution for improving Single-Instruction Multiple-Thread branching efficiency. Unlike current SIMT hardware branching architectures, this hardware-software solution allows programmers the ability to fine tune branching behavior for their application or allow the compiler to implement a generic software solution. To support a wide range of SIMT applications with different control flow properties, three branching methods are implemented in hardware with configurable software instructions. The three branching methods are the contemporary Post-Dominator Re-convergence that is currently implemented in SIMT Processors, a proposed Hyperthreaded SIMT Processor cores for maintaining statically allocated thread warps and a proposed Dynamic Micro-Kernels that modified thread warps during run-time execution. Each of the implemented branching methods have their strengths and weaknesses and result in different performance improvements depending on the application. SIMT hyper-threading turns a single SIMT Processor core into multiple Virtual Processors. These Virtual Processors run divergent control flow paths in parallel from threads in the same warp. Controlling how the Virtual Processor cores are created is done using a per-warp stack that is managed through software instructions. Dynamic Micro-Kernels creates new threads at run-time to execute divergent control flow paths instead of using branching instructions. A spawn instruction is used to create threads at run-time and once created are placed into new warps with similar threads follow the same control flow path. This thesis's integrated hardware-software branching architectures are evaluated using different realistic benchmarks with varying control flow divergence. Synthetic benchmarks are also used for evaluation and are designed to test specific branching conditions and isolate common branching behaviors. Each of the hardware implemented branching solutions are tested in isolation using different software algorithms. Algorithms are designed for general purpose use or to target specific types of branching conditions. Results shows improved performance for divergent applications and using different software algorithms will affect performance.
Junlong Zhou - One of the best experts on this subject based on the ideXlab platform.
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thermal aware correlated two level scheduling of real time tasks with reduced Processor energy on heterogeneous mpsocs
Journal of Systems Architecture, 2018Co-Authors: Junlong Zhou, Jianming Yan, Kun Cao, Yanchao Tan, Tongquan Wei, Mingsong Chen, Gongxuan Zhang, Xiaodao ChenAbstract:Abstract With the exponential increase in power density and the relentless scaling of transistors in VLSI circuits over the past decades, modern high-performance Processors fall into a predicament of high energy consumption and elevated chip temperature. Such increased energy consumption and chip temperature could induce significant economic, ecological, and technical problems. Thus, energy-efficient task scheduling with thermal consideration has become a pressing research issue in sustainable computing systems, especially for battery-powered real-time embedded systems with limited cooling techniques. This paper tackles the above challenge through scheduling tasks leveraging correlated optimizations at two different scales. Precisely, a two-level thermal-aware energy-efficient scheduling algorithm for real-time tasks on DVFS-enabled heterogeneous MPSoC systems is developed considering the constraints of task deadlines, task precedences, and chip peak temperature limit. At the Processor level, a multi-Processor model supporting dynamic voltage/frequency scaling is transformed to a Virtual multi-Processor model supporting only one fixed frequency level. At the core level, real-time tasks are assigned to individual cores of the Virtual Processor under the constraints of task precedence and peak temperature limit. Through nicely interleaving optimizations at both levels, high quality task scheduling solutions can be computed efficiently. Extensive simulations of synthetic real-time tasks and real-life benchmarks are performed to validate the proposed algorithm. Experimental results demonstrate the effectiveness of the proposed algorithm as compared to the benchmarking schemes.
Xiaodao Chen - One of the best experts on this subject based on the ideXlab platform.
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thermal aware correlated two level scheduling of real time tasks with reduced Processor energy on heterogeneous mpsocs
Journal of Systems Architecture, 2018Co-Authors: Junlong Zhou, Jianming Yan, Kun Cao, Yanchao Tan, Tongquan Wei, Mingsong Chen, Gongxuan Zhang, Xiaodao ChenAbstract:Abstract With the exponential increase in power density and the relentless scaling of transistors in VLSI circuits over the past decades, modern high-performance Processors fall into a predicament of high energy consumption and elevated chip temperature. Such increased energy consumption and chip temperature could induce significant economic, ecological, and technical problems. Thus, energy-efficient task scheduling with thermal consideration has become a pressing research issue in sustainable computing systems, especially for battery-powered real-time embedded systems with limited cooling techniques. This paper tackles the above challenge through scheduling tasks leveraging correlated optimizations at two different scales. Precisely, a two-level thermal-aware energy-efficient scheduling algorithm for real-time tasks on DVFS-enabled heterogeneous MPSoC systems is developed considering the constraints of task deadlines, task precedences, and chip peak temperature limit. At the Processor level, a multi-Processor model supporting dynamic voltage/frequency scaling is transformed to a Virtual multi-Processor model supporting only one fixed frequency level. At the core level, real-time tasks are assigned to individual cores of the Virtual Processor under the constraints of task precedence and peak temperature limit. Through nicely interleaving optimizations at both levels, high quality task scheduling solutions can be computed efficiently. Extensive simulations of synthetic real-time tasks and real-life benchmarks are performed to validate the proposed algorithm. Experimental results demonstrate the effectiveness of the proposed algorithm as compared to the benchmarking schemes.
Xin Wei - One of the best experts on this subject based on the ideXlab platform.
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a tracing approach to process migration for Virtual machine based on multicore platform
International Conference on Algorithms and Architectures for Parallel Processing, 2010Co-Authors: Liang Zhang, Yuebin Bai, Xin WeiAbstract:Recently, multicore Processor and Virtualization become popular in research and application And an even newer tendency is to deploy Virtualization on multicore Processor platform This means on a physical server, several isolated and high performance Virtual environments are provided, and concurrent program has a chance to run in a multicore Virtualized environment But most Virtual Processor (VCPU) scheduler in VMM is not efficient in scheduling concurrent program with synchronization And we have developed a VMM with a new VCPU scheduler to reduce the synchronization cost in some scenarios As a component of this VMM, we need an approach to trace the processes migration in Virtual machine and the mapping relationship between VCPUs and cores of physical Processor to verify whether the new scheduler is effective and consistent with our initial idea In this paper, we present such an approach and a demo Process Migration Tracing Engine for monitoring the migration of process on VCPU(s) and VCPU(s) on the cores of physical Processor based on Linux 2.6 and Xen 3.2 We evaluate the impact of the engine on system performance and the results shows that this tracing approach and the tracing engine are effective and efficient.
