The Experts below are selected from a list of 300 Experts worldwide ranked by ideXlab platform
Massoud Pedram - One of the best experts on this subject based on the ideXlab platform.
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ISPD - Robust design of power-efficient VLSI Circuits
Proceedings of the 2011 international symposium on Physical design - ISPD '11, 2011Co-Authors: Massoud PedramAbstract:Digital information management is the key enabler for the unparalleled rise in productivity and efficiency gains experienced by the world economies. Computing and information processing systems are important elements of the world's digital infrastructure by providing ever-present and ever-increasing general purpose and data-driven processing and storage capabilities for both wired and mobile users. As such, they are also significant drivers of economic growth and social change. However, continued expansion of computing and information processing systems is now hindered by their unsustainable and rising power needs, with associated electrical energy costs and peak power draw requirements. Moreover governments, people, and corporations are becoming increasingly concerned about the environmental impact of these systems i.e., their carbon footprint. Separately from all this, with the increasing levels of variability in the characteristics of nanoscale CMOS devices and on-chip interconnects and continued uncertainty in the operating conditions of VLSI Circuits, achieving power efficiency and high performance in computing and information processing systems under process, voltage, and temperature variations as well as interconnect wear-out and device aging has become a daunting, yet vital, task. It is against this backdrop of rising power demands and energy costs as well as increased device- and circuit-level variability and aging effects that I present a number of best practices and methods for improving the power-performance efficiency of VLSI Circuits and systems. The reviewed techniques range from dynamic power management to design of power-aware Circuits, and from power/clock gating to leakage power minimization. A key issue to be addressed is how to deal with process and environment-induced variability of circuit parameters through statistical modeling and robust optimization and how to manage uncertainty about the workload and input data characteristics through observations and closed feedback loop control.
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thermal modeling analysis and management in VLSI Circuits principles and methods
Proceedings of the IEEE, 2006Co-Authors: Massoud Pedram, Shahin NazarianAbstract:The growing packing density and power consumption of very large scale integration (VLSI) Circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI Circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI Circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods
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ICCD - Analysis and reduction of capacitive coupling noise in high-speed VLSI Circuits
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, 1Co-Authors: Payam Heydari, Massoud PedramAbstract:Scaling the minimum feature size of VLSI Circuits to sub-quarter micron and its clock frequency to 2 GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated Circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI Circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise. Experiments show that our analytical predictions are at least two times better than the previous models in terms of the prediction accuracy. More precisely, experimental results show that the maximum error of our predictions is less than 10% while the average error is only 4%. Finally, based on the proposed analytical models, we discuss the effects of transistor sizing and buffering on crosstalk noise reduction in VLSI Circuits.
Keshab K Parhi - One of the best experts on this subject based on the ideXlab platform.
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low power synthesis of dual threshold voltage cmos VLSI Circuits
International Symposium on Low Power Electronics and Design, 1999Co-Authors: Vijay Sundararajan, Keshab K ParhiAbstract:The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI Circuits. With the supply voltage at 1 V and threshold voltage as low as 0.2 V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption. We present a near-optimal approach to synthesize low static power CMOS VLSI Circuits with two threshold voltages that reduces power consumption compared with a previous approach by up to 29.45%. Also, presented is a technique which finds static power optimal configurations for CMOS VLSI Circuits when an arbitrary number of threshold voltages are allowed.
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ISLPED - Low power synthesis of dual threshold voltage CMOS VLSI Circuits
Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED '99, 1999Co-Authors: Vijay Sundararajan, Keshab K ParhiAbstract:The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI Circuits. With the supply voltage at 1 V and threshold voltage as low as 0.2 V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption. We present a near-optimal approach to synthesize low static power CMOS VLSI Circuits with two threshold voltages that reduces power consumption compared with a previous approach by up to 29.45%. Also, presented is a technique which finds static power optimal configurations for CMOS VLSI Circuits when an arbitrary number of threshold voltages are allowed.
Jeffrey Gealow - One of the best experts on this subject based on the ideXlab platform.
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Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits
IEEE Journal of Solid-State Circuits, 2015Co-Authors: Jeffrey Gealow, Masato MotomuraAbstract:The 21 papers in this special issue were originally presented at the 28th Symposium on VLSI Circuits, held June 10-13, 2014, in Honolulu, Hawaii, USA.
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Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits
IEEE Journal of Solid-State Circuits, 2014Co-Authors: Hideyuki Kabuo, Jeffrey GealowAbstract:The 23 papers in this special issue were originally presented at the 2013 Symposium on VLSI Circuits, held in Kyoto, Japan, on June 12-14, 2013.
Masato Motomura - One of the best experts on this subject based on the ideXlab platform.
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Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Masato Motomura, Andreia CathelinAbstract:The papers in this special section were presented at the 29th Symposium on VLSI Circuits, held on June 16–19, 2015 at the Rihga Royal Hotel Kyoto, Japan. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers.
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Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits
IEEE Journal of Solid-State Circuits, 2015Co-Authors: Jeffrey Gealow, Masato MotomuraAbstract:The 21 papers in this special issue were originally presented at the 28th Symposium on VLSI Circuits, held June 10-13, 2014, in Honolulu, Hawaii, USA.
Hideyuki Kabuo - One of the best experts on this subject based on the ideXlab platform.
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Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits
IEEE Journal of Solid-State Circuits, 2014Co-Authors: Hideyuki Kabuo, Jeffrey GealowAbstract:The 23 papers in this special issue were originally presented at the 2013 Symposium on VLSI Circuits, held in Kyoto, Japan, on June 12-14, 2013.
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Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits
IEEE Journal of Solid-State Circuits, 2013Co-Authors: Hideyuki KabuoAbstract:This issue of the IEEE JOURNAL OF SOLID-STATE Circuits highlights some of the best papers from the 2012 Symposium on VLSI Circuits, which was held at the Hilton Hawaiian Village, Honolulu, Hawaii, USA, June 13-15, 2012. In 2012, the Symposium held its 26th meeting on state-of-the-art topics important to VLSI circuit and system designers, as well as device and process technology experts. Industry and academia from all over the world presented papers at the Symposium highlighting important technical contributions and recent advances in VLSI circuit design. The Symposium on VLSI Circuits received 386 submissions from 22 countries of which 97 papers were selected for presentation, covering a range of topics on digital, memory, analog, wireless and wireline communication Circuits. From these presentations, the committee has selected 19 outstanding papers as highlights of the 2012 Symposium for publication in this issue of the Journal. They are presented with greater detail than in the Symposium digest. These papers were subject to the standard Journal review and rigorous referee process. We enjoyed working with the authors on these papers, and we certainly hope that the technical details presented in these papers will be valuable and enjoyable to the Journal reader.
