The Experts below are selected from a list of 1809 Experts worldwide ranked by ideXlab platform
Carl Ebeling - One of the best experts on this subject based on the ideXlab platform.
-
a type architecture for hybrid micro parallel computers
Field-Programmable Custom Computing Machines, 2006Co-Authors: Benjamin Ylvisaker, Brian Van Essen, Carl EbelingAbstract:Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics remains challenging. The difficulty arises in part from the lack of an agreed upon computational model and family of programming languages. In addition, moving algorithms into hardware is an arcane art far removed from the experience of most programmers. To address this challenge, we present a new type architecture, an abstract model analogous to the Von Neumann Machine for sequential computers, that can serve as common ground for algorithm designers, language designers, and hardware architects. We show that many parallel architectures, including platform FPGAs, are implementations of this type architecture. Using examples from a variety of application domains, we show how algorithms can be analyzed to estimate their performance on implementations of this type architecture. This analysis is done without having to delve into the details of any architecture in particular. Finally, we describe some of the common features of languages designed for expressing micro-parallelism, highlighting connections with the type architecture.
-
a type architecture for hybrid micro parallel computers
Field Programmable Gate Arrays, 2006Co-Authors: Benjamin Ylvisaker, Brian Van Essen, Carl EbelingAbstract:Programmable spatial fabrics, such as FPGAs, can provide some of the performance and efficiency benefits of custom hardware while retaining the low cost and flexibility of reprogrammable architectures. However, these fine-grained parallel architectures still have not been as widely adopted as many believe they could be for computationally intensive applications. The problem is two-fold: First, most applications contain substantial amounts of mostly sequential code that does not execute efficiently on a spatial fabric. Second, programming spatial architectures still requires some knowledge of the arcane arts of hardware engineering.Recently, hybrid processors that integrate a sequential processor with a spatial fabric have become prevalent. While hybrid computers ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics, remains challenging. Part of the difficulty lies in the lack of a commonly agreed upon computational model and family of programming languages.To address this challenge, we are developing a new type architecture--an abstract model analogous to the Von Neumann Machine for sequential computers--that can serve as common ground for algorithm designers, language designers, and hardware architects. We show how this model applies to several relevant architectures, and present examples of how it can effectively inform algorithm, language, and hardware design, thereby improving the programmability of hybrid processors.
Benjamin Ylvisaker - One of the best experts on this subject based on the ideXlab platform.
-
a type architecture for hybrid micro parallel computers
Field-Programmable Custom Computing Machines, 2006Co-Authors: Benjamin Ylvisaker, Brian Van Essen, Carl EbelingAbstract:Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics remains challenging. The difficulty arises in part from the lack of an agreed upon computational model and family of programming languages. In addition, moving algorithms into hardware is an arcane art far removed from the experience of most programmers. To address this challenge, we present a new type architecture, an abstract model analogous to the Von Neumann Machine for sequential computers, that can serve as common ground for algorithm designers, language designers, and hardware architects. We show that many parallel architectures, including platform FPGAs, are implementations of this type architecture. Using examples from a variety of application domains, we show how algorithms can be analyzed to estimate their performance on implementations of this type architecture. This analysis is done without having to delve into the details of any architecture in particular. Finally, we describe some of the common features of languages designed for expressing micro-parallelism, highlighting connections with the type architecture.
-
a type architecture for hybrid micro parallel computers
Field Programmable Gate Arrays, 2006Co-Authors: Benjamin Ylvisaker, Brian Van Essen, Carl EbelingAbstract:Programmable spatial fabrics, such as FPGAs, can provide some of the performance and efficiency benefits of custom hardware while retaining the low cost and flexibility of reprogrammable architectures. However, these fine-grained parallel architectures still have not been as widely adopted as many believe they could be for computationally intensive applications. The problem is two-fold: First, most applications contain substantial amounts of mostly sequential code that does not execute efficiently on a spatial fabric. Second, programming spatial architectures still requires some knowledge of the arcane arts of hardware engineering.Recently, hybrid processors that integrate a sequential processor with a spatial fabric have become prevalent. While hybrid computers ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics, remains challenging. Part of the difficulty lies in the lack of a commonly agreed upon computational model and family of programming languages.To address this challenge, we are developing a new type architecture--an abstract model analogous to the Von Neumann Machine for sequential computers--that can serve as common ground for algorithm designers, language designers, and hardware architects. We show how this model applies to several relevant architectures, and present examples of how it can effectively inform algorithm, language, and hardware design, thereby improving the programmability of hybrid processors.
Brian Van Essen - One of the best experts on this subject based on the ideXlab platform.
-
a type architecture for hybrid micro parallel computers
Field-Programmable Custom Computing Machines, 2006Co-Authors: Benjamin Ylvisaker, Brian Van Essen, Carl EbelingAbstract:Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics remains challenging. The difficulty arises in part from the lack of an agreed upon computational model and family of programming languages. In addition, moving algorithms into hardware is an arcane art far removed from the experience of most programmers. To address this challenge, we present a new type architecture, an abstract model analogous to the Von Neumann Machine for sequential computers, that can serve as common ground for algorithm designers, language designers, and hardware architects. We show that many parallel architectures, including platform FPGAs, are implementations of this type architecture. Using examples from a variety of application domains, we show how algorithms can be analyzed to estimate their performance on implementations of this type architecture. This analysis is done without having to delve into the details of any architecture in particular. Finally, we describe some of the common features of languages designed for expressing micro-parallelism, highlighting connections with the type architecture.
-
a type architecture for hybrid micro parallel computers
Field Programmable Gate Arrays, 2006Co-Authors: Benjamin Ylvisaker, Brian Van Essen, Carl EbelingAbstract:Programmable spatial fabrics, such as FPGAs, can provide some of the performance and efficiency benefits of custom hardware while retaining the low cost and flexibility of reprogrammable architectures. However, these fine-grained parallel architectures still have not been as widely adopted as many believe they could be for computationally intensive applications. The problem is two-fold: First, most applications contain substantial amounts of mostly sequential code that does not execute efficiently on a spatial fabric. Second, programming spatial architectures still requires some knowledge of the arcane arts of hardware engineering.Recently, hybrid processors that integrate a sequential processor with a spatial fabric have become prevalent. While hybrid computers ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics, remains challenging. Part of the difficulty lies in the lack of a commonly agreed upon computational model and family of programming languages.To address this challenge, we are developing a new type architecture--an abstract model analogous to the Von Neumann Machine for sequential computers--that can serve as common ground for algorithm designers, language designers, and hardware architects. We show how this model applies to several relevant architectures, and present examples of how it can effectively inform algorithm, language, and hardware design, thereby improving the programmability of hybrid processors.
Strother J Moore - One of the best experts on this subject based on the ideXlab platform.
-
proof pearl proving a simple Von Neumann Machine turing complete
Interactive Theorem Proving, 2014Co-Authors: Strother J MooreAbstract:In this paper we sketch an ACL2-checked proof that a simple but unbounded Von Neumann Machine model is Turing Complete, i.e., can do anything a Turing Machine can do. The project formally revisits the roots of computer science. It requires re-familiarizing oneself with the definitive model of computation from the 1930s, dealing with a simple “modern” Machine model, thinking carefully about the formal statement of an important theorem and the specification of both total and partial programs, writing a verifying compiler, including implementing an X86-like call/return protocol and implementing computed jumps, codifying a code proof strategy, and a little “creative” reasoning about the non-termination of two Machines.
Monsalve Diaz, Jose M. - One of the best experts on this subject based on the ideXlab platform.
-
Sequential Codelet Model: A SuperCodelet Program Execution Model and Architecture
University of Delaware, 2021Co-Authors: Monsalve Diaz, Jose M.Abstract:In sequential computers, the Instruction Set Architecture provides a clear division between software and hardware. Separation of software and hardware through a well defined contract enabled decades long of seamless evolution of computer systems. The end of Dennard's scaling and slow down of Moore's law has forced architects to abandon purely sequential architectures in favor of parallel/distributed and heterogeneous systems. The new era represents a new spring of computer architectures. However, the ISA contract has been broken. It is mandatory to reconcile the abstraction between hardware and software in order to recover performance, portability, and programmability. Sequential architectures take advantage of Instruction level parallelism to overlap the execution of instructions. These techniques use dataflow to implicitly perform side-effect free parallel execution of code. On the other hand, parallel programming often requires explicit reasoning of workload distribution, communication, memory synchronization and worker management. This thesis proposes the Sequential Codelet Model, a program execution model for parallel, heterogeneous and distributed execution of programs. It defines a Machine abstraction (namely hierarchical Von Neumann Machine), that recognizes the natural hierarchical structure of computer systems. Programming of the Machine uses a hierarchical imperative programming model reassembling an Instruction Set Architecture at each level. A Codelet is the name given to an ``instruction'' of a level, as expressed in terms of instructions of the level below. By means of Instruction Level Parallelism inspired techniques, parallel/distributed execution of programs is achieved. The final system leverages the vast progress made for sequential computers. Finally, We present a the Super Codelet Architecture, a possible realization of the Sequential Codelet Model
