Wafer Flatness

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Randal K Goodall - One of the best experts on this subject based on the ideXlab platform.

  • Quantification of Wafer printability improvements with scanning steppers using new Flatness metrics
    Metrology Inspection and Process Control for Microlithography XIII, 1999
    Co-Authors: Yiorgos Kostoulas, Sahra Berman Tanikawa, David Kallus, Randal K Goodall
    Abstract:

    The prevailing models for Wafer Flatness provide simulation of contact lithography via global Flatness parameters such as GBIR, GFLD and GFLR and step-and-repeat lithography. Steppers are modeled as either non-leveling, global leveling or site-by-site leveling. As device critical dimensions shrink and lithographic depth of field is tightened, optical lithography steppers move to new exposure methods. It is imperative, therefore the Wafer geometry characterization follows suit in modeling the operation of the new generation steppers. In this work we examine the capabilities of four sets of 200 mm Wafers - each from a different manufacturing process - to satisfy the emerging needs of the 180, 150 and 130 nm features. We use both full-site and scanning stepper metrics and our results show increased yield for scanner vs. full site exposure for the same Flatness limit. In addition, we show that for full-site exposure, yield is reduced with increasing field length.

  • Wafer Flatness modeling for scanning steppers
    Proceedings of SPIE the International Society for Optical Engineering, 1996
    Co-Authors: Randal K Goodall, Howard R Huff
    Abstract:

    Model-based analysis is used to explain previous observations regarding the distributional form and numeric relationships of several key lithographic Flatness quality metrics for silicon Wafers. The dominant relationships are controlled by longer wavelength (tens of millimeters) surface topography, while the distribution shapes are controlled by shorter wavelength (few millimeters) topography. A lithographic Flatness modeling framework is introduced which can provide guidance for specification of silicon Wafer Flatness for ULSI IC products. New site Flatness models show that, compared to a full-field stepper, a scanning stepper can effect improved Flatness performance from Wafers of similar quality.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

  • Advanced photolithographic process modeling and characterization via Wafer Flatness measurements
    Integrated Circuit Metrology Inspection and Process Control VIII, 1994
    Co-Authors: Satyendra S. Sethi, Randal K Goodall, Sagar M. Pushpala, Terry L. Von Salza Brown, Clifford H. Takemoto, Gabriel M. Li, James L. Kawski, H. Noguchi
    Abstract:

    In this work critical dimension (CD) and site focal plane deviation (SFPD) measurements were made on a patterned resist test structure with 0.8 micron dense lines with a pitch of 1.6 micrometers . The CD and SFPD were tracked through all critical Wafer processing steps. The range in SFPD was negligible throughout front end processing, with average SFPDs less than 0.25 microns. Significant increase in the mean and variance of SFPD was observed at later process modules. An increase in the SFPD directly reduces the focus budget, resulting in an increase in the variation of the CD across a field as well as a degradation of the resist profile. Within-field CD variation (3 sigma) for a SFPD of 0.05 micrometers was observed to be less than 0.03 micrometers (30 measurement sites within a field) whereas the three sigma CD variation for a SFPD of 3.8 micrometers was observed to be 0.45 micrometers . Two-dimensional and 3-D graphical correlations are presented, and the use of the SFPD/CD correlation technique to photolithographic process optimization is discussed.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

  • Characterization of stepper chuck performance
    Integrated Circuit Metrology Inspection and Process Control VII, 1993
    Co-Authors: Randal K Goodall, Frances P. Alvarez
    Abstract:

    A new metrology method is described which is capable of extracting information about the Flatness and performance of the vacuum chuck which holds the Wafer in a photolithographic stepper. The method is based on a comparison of the Wafer Flatness as measured by the stepper and the Wafer Flatness as measured by a thickness-based Flatness metrology system. The Flatness datamaps for one Wafer are subtracted using ensemble mathematics to yield a stepper chuck signature datamap. Signatures for several Wafers are ensemble averaged to test for statistical validity. Stepper and Flatness metrology data as well as statistical signatures are presented. Wafer and operational dependencies are discussed. The signature has potential use in the tracking of chuck wear and the feeding forward of Flatness information to stepper control systems.

  • Data point selection for site qualification of Wafers for ULSI lithography
    Integrated Circuit Metrology Inspection and Process Control IV, 1990
    Co-Authors: Randal K Goodall, Noel S. Poduje
    Abstract:

    Advanced, automated Wafer Flatness characterization systems allow flexibility in emulating lithographic systems. Other considerations related to the interaction of an individual characterization system with a lithographic application are becoming more critical with shrinking device geometries. Specifically, all automatic Flatness characterization systems use an array of discrete, sampled data points across the surface of the Wafer. This paper will show that the definition and location of these points influences the measured site Flatness. Situations leading to error are modeled. A distinction is made between the sample array (the points at which data is acquired) and a second analysis array (derived from the first) used for calculation of the site Flatness. It is shown that, assuming the sample array meets the Nyquist criteria for the Wafer topography of interest, the analysis array may be optimized for that application. Results from measurements made on typical polished Wafers are related to the models. A strategy is presented for optimization of the analysis array.

R W Potter - One of the best experts on this subject based on the ideXlab platform.

  • correlation of 150 mm p p epitaxial silicon Wafer Flatness parameters for deep submicron applications
    Journal of The Electrochemical Society, 1993
    Co-Authors: H R Huff, G H Popham, R W Potter
    Abstract:

    Experimental data for 426 P/P + epitaxial Wafers from two suppliers are presented for both front-surface and back-surface site Flatness parameters SFQR, SFQD, SBIR, SBID and global data GFLR, GFLD, GF3R, GF3D, GBIR, taper, bow, warp, and sori. Correlations and recommendations among the various Flatness parameters are presented to gain insight into the characteristic Flatness parameters required for an accurate description of Wafer Flatness. The recommended Flatness parameters for measurement are GFLR, GBIR, SFQR, and warp

Howard R Huff - One of the best experts on this subject based on the ideXlab platform.

  • Competitive assessment of 200-mm epitaxial silicon Wafer Flatness
    Metrology Inspection and Process Control for Microlithography XII, 1998
    Co-Authors: Howard R Huff, D. W. Mccormack
    Abstract:

    The Flatness data indicates all suppliers are capable of supporting the 250 nm technology generation while several suppliers are already capable of supporting the 180 nm technology generation. It appears that individual parameter 300 mm polished Wafer data are comparable with state-of-the- art and, indeed, may even be better than for 200 mm epitaxial Wafers. Continued improvements in the control of the magnitude, tolerance and uniformity of silicon Wafers is essential. A steep gradient in the learning curve is being pursued by all suppliers, especially for 300 mm Wafers. However, it is also critical to balance the ''best Wafer possible' against the cost-o-ownership (CoO) opportunity of not driving silicon requirements to the detection limit or ultimate tool resolution but to some less stringent and optimized value.

  • Wafer Flatness modeling for scanning steppers
    Proceedings of SPIE the International Society for Optical Engineering, 1996
    Co-Authors: Randal K Goodall, Howard R Huff
    Abstract:

    Model-based analysis is used to explain previous observations regarding the distributional form and numeric relationships of several key lithographic Flatness quality metrics for silicon Wafers. The dominant relationships are controlled by longer wavelength (tens of millimeters) surface topography, while the distribution shapes are controlled by shorter wavelength (few millimeters) topography. A lithographic Flatness modeling framework is introduced which can provide guidance for specification of silicon Wafer Flatness for ULSI IC products. New site Flatness models show that, compared to a full-field stepper, a scanning stepper can effect improved Flatness performance from Wafers of similar quality.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

  • Experimental assessment of 150-mm P/P+ epitaxial silicon Wafer Flatness for deep-submicron applications
    Integrated Circuit Metrology Inspection and Process Control V, 1991
    Co-Authors: Howard R Huff, Harrison Weed
    Abstract:

    An experimental assessment of Wafer Flatness for 150 mm P/P+ epitaxial silicon Wafers is presented to illustrate the use of graphical and analytical statistical techniques to both characterize and determine methods to reduce the variation in Wafer Flatness. This approach is applied to the chucked Local Total Indicator Reading (LTIR) site least squares front-reference plane for 354 P/P+ Wafers and 144 P-type Wafers from three suppliers measured over a range of site sizes (15 mm X 15 mm, 20 mm X 20 mm, 25 mm X 25 mm, and 20 mm X 30 mm). The objective is to ascertain the extent to which the lens total indicator range budget (taken as 1.1 micrometers as a figure of merit), is utilized by the silicon material. After taking into account estimates of the circuit topography and the lithographic machine detractors, an upper bound of 0.52 micrometers for the silicon LTIR was determined by an RMS analysis and a lower bound of 0.30 micrometers was taken as an approximation to a linear analysis. Histogram, cumulative frequency plots, and boxplot analysis for the sites on the Wafers are presented. The importance of correcting for 'abnormal' site locations on the gauge chuck is noted. The percent variance components of Flatness within a Wafer, Wafer to Wafer in an epi run, epi run to epi run, polish lot to polish lot, and shipment to shipment is also presented. The source of the epi Wafer percent variability appears to reside in the polished Wafer substrate rather than be intrinsic to the epi process per se by comparing 'before' and 'after' epi Wafer LTIR data.

Jun Shimizu - One of the best experts on this subject based on the ideXlab platform.

  • Design of Digital Filters for Si Wafer Surface Profile Measurement - Noise Reduction by Wavelet Transform -
    Key Engineering Materials, 2010
    Co-Authors: Kazutaka Nonomura, Libo Zhou, Jun Shimizu
    Abstract:

    Recently in semiconductor industry, production of ever flatter, thinner and larger silicon Wafers are required to fulfill the demands of high-density packaging and cost reduction. In geometric evaluation of Si Wafers, according to SEMI (Semiconductor Equipment and Materials International) standards, the required Wafer Flatness approaches to the 22 nanometers by year 2016 [1]. For such application, uncertainty of measured data is encountered as a severe problem because high resolution instrument always incorporate a certain degree of noise. In order to precisely evaluate the Wafer profile, it is essential to remove the noise from the measured data. Described in this paper is design and development of digital filters for denoising. Compared to the conventional low-pass filters, the developed filter by use of wavelet transform not only provides better performance of decomposition in the spatial frequency domain, but also offers the new capability of denoising in amplitude domain.

  • Design of Digital Filters for Si Wafer Surface Profile Measurement – Noise Reduction by Lifting Scheme Wavelet Transform
    Advanced Materials Research, 2010
    Co-Authors: Kazutaka Nonomura, Libo Zhou, Jun Shimizu, Hirotaka Ojima
    Abstract:

    Recently in semiconductor industry, production of ever flatter, thinner and larger silicon Wafers are required to fulfill the demands of high-density packaging and cost reduction. In geometric evaluation of Si Wafers, according to SEMI (Semiconductor Equipment and Materials International) standards, the required Wafer Flatness approaches to the 22 nanometers by year 2016 [1]. For such application, uncertainty of measured data is encountered as a severe problem because the requirement has met the limit of available instrument in terms of resolution and reliability. In order to precisely evaluate the Wafer profile, it is essential to remove the noise from the measured data. Described in this paper is design and development of digital filters for denoising. In previous paper, digital filters for denoising with Haar wavelet transform are described. In this paper, the new filters by use of 2nd generation wavelet transform (lifting scheme) are proposed and show better performance of decomposition in the spatial frequency domain and amplitude domain.

  • Development of atomic level GMM positioning/alignment system for driving a gigantic weight spindle - Core technology for advanced ??300mm Si Wafer ultraprecision machine tool
    Seimitsu Kogaku Kaishi Journal of the Japan Society for Precision Engineering, 2003
    Co-Authors: Hiroshi Eda, Hirotami Nakano, Ryou Kondo, Teruo Mori, Libo Zhou, Jun Shimizu
    Abstract:

    In order to achieve damage free surface of Si Wafer by a single step grinding process, each cutting edge should be controlled below the critical depth of cut. Additionally, the achievable Wafer Flatness by infeed grinding significantly depends upon the alignment between the Wafer and the wheel. As one of the core technologies of an integrated manufacturing system for φ300mm silicon Wafer, a GMM (giant magnetostrictive material) actuated positioning/alignment device has been designed and developed to control half a ton payload at A resolution over the several um stroke range (about 5μm) and simultaneously to align the co-axis between the work and wheel at the resolution of 0.1". This paper describes the design of the GMM actuator and elastically deformable mechanism for position/alignment, the control schemes and on-situ performance.

H R Huff - One of the best experts on this subject based on the ideXlab platform.

  • correlation of 150 mm p p epitaxial silicon Wafer Flatness parameters for deep submicron applications
    Journal of The Electrochemical Society, 1993
    Co-Authors: H R Huff, G H Popham, R W Potter
    Abstract:

    Experimental data for 426 P/P + epitaxial Wafers from two suppliers are presented for both front-surface and back-surface site Flatness parameters SFQR, SFQD, SBIR, SBID and global data GFLR, GFLD, GF3R, GF3D, GBIR, taper, bow, warp, and sori. Correlations and recommendations among the various Flatness parameters are presented to gain insight into the characteristic Flatness parameters required for an accurate description of Wafer Flatness. The recommended Flatness parameters for measurement are GFLR, GBIR, SFQR, and warp