The Experts below are selected from a list of 205632 Experts worldwide ranked by ideXlab platform
Shingo Yoshizawa - One of the best experts on this subject based on the ideXlab platform.
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a stochastic flash a to d Converter with dynamic element matching technique
International Symposium on Communications and Information Technologies, 2015Co-Authors: Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:This paper discusses and compares the effects of dynamic element matching (DEM) methods applied to the stochastic flash A-to-D Converter (SFADC) to improve its linearity and noise behavior. Simulation results have shown that the application of DEM greatly improves linearity and SNDR behavior, and a simple random barrel-shift type of DEM is enough for 6-bit resolution case.
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fpga implementation of stochastic flash a to d Converter and its evaluation
International Symposium on Communications and Information Technologies, 2015Co-Authors: Hisato Takehata, Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:We report a hardware implementation of stochastic flash A-to-D Converter (SFADC) with dynamic element matching (DEM) technique. For fast prototyping, the SFADC hardware was implemented on an FPGA board with 64 on-chip inverters using as comparators. The DEM circuit is implemented by analog multiplexer, which is put in front of the main SFADC. Measured histogram of comparator offset voltage resembles the normal distribution, but actually it is not, according to χ2 test result for 5% p-value. However, the linearization and DEM works nicely and SFDR is improved more than 5 dB by proposed SFADC with DEM, even for non-normal distribution.
Toshiki Sugimoto - One of the best experts on this subject based on the ideXlab platform.
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a stochastic flash a to d Converter with dynamic element matching technique
International Symposium on Communications and Information Technologies, 2015Co-Authors: Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:This paper discusses and compares the effects of dynamic element matching (DEM) methods applied to the stochastic flash A-to-D Converter (SFADC) to improve its linearity and noise behavior. Simulation results have shown that the application of DEM greatly improves linearity and SNDR behavior, and a simple random barrel-shift type of DEM is enough for 6-bit resolution case.
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fpga implementation of stochastic flash a to d Converter and its evaluation
International Symposium on Communications and Information Technologies, 2015Co-Authors: Hisato Takehata, Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:We report a hardware implementation of stochastic flash A-to-D Converter (SFADC) with dynamic element matching (DEM) technique. For fast prototyping, the SFADC hardware was implemented on an FPGA board with 64 on-chip inverters using as comparators. The DEM circuit is implemented by analog multiplexer, which is put in front of the main SFADC. Measured histogram of comparator offset voltage resembles the normal distribution, but actually it is not, according to χ2 test result for 5% p-value. However, the linearization and DEM works nicely and SFDR is improved more than 5 dB by proposed SFADC with DEM, even for non-normal distribution.
Hiroshi Tanimoto - One of the best experts on this subject based on the ideXlab platform.
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a stochastic flash a to d Converter with dynamic element matching technique
International Symposium on Communications and Information Technologies, 2015Co-Authors: Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:This paper discusses and compares the effects of dynamic element matching (DEM) methods applied to the stochastic flash A-to-D Converter (SFADC) to improve its linearity and noise behavior. Simulation results have shown that the application of DEM greatly improves linearity and SNDR behavior, and a simple random barrel-shift type of DEM is enough for 6-bit resolution case.
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fpga implementation of stochastic flash a to d Converter and its evaluation
International Symposium on Communications and Information Technologies, 2015Co-Authors: Hisato Takehata, Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:We report a hardware implementation of stochastic flash A-to-D Converter (SFADC) with dynamic element matching (DEM) technique. For fast prototyping, the SFADC hardware was implemented on an FPGA board with 64 on-chip inverters using as comparators. The DEM circuit is implemented by analog multiplexer, which is put in front of the main SFADC. Measured histogram of comparator offset voltage resembles the normal distribution, but actually it is not, according to χ2 test result for 5% p-value. However, the linearization and DEM works nicely and SFDR is improved more than 5 dB by proposed SFADC with DEM, even for non-normal distribution.
Hisato Takehata - One of the best experts on this subject based on the ideXlab platform.
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fpga implementation of stochastic flash a to d Converter and its evaluation
International Symposium on Communications and Information Technologies, 2015Co-Authors: Hisato Takehata, Toshiki Sugimoto, Hiroshi Tanimoto, Shingo YoshizawaAbstract:We report a hardware implementation of stochastic flash A-to-D Converter (SFADC) with dynamic element matching (DEM) technique. For fast prototyping, the SFADC hardware was implemented on an FPGA board with 64 on-chip inverters using as comparators. The DEM circuit is implemented by analog multiplexer, which is put in front of the main SFADC. Measured histogram of comparator offset voltage resembles the normal distribution, but actually it is not, according to χ2 test result for 5% p-value. However, the linearization and DEM works nicely and SFDR is improved more than 5 dB by proposed SFADC with DEM, even for non-normal distribution.
Gabor C. Temes - One of the best experts on this subject based on the ideXlab platform.
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oversampling delta sigma data Converters theory design and simulation
1992Co-Authors: James C. Candy, Gabor C. TemesAbstract:Preface. Introduction. Oversampling Methods for A/D and D/A Conversion (J. Candy & G. Temes). BASIC THEORY AND ANALYSIS. An Analysis of Nonlinear Behavior in Delta-Sigma Modulators (S. Ardalan & J. Paulos). A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters (J. Candy). The Structure of Quantization Noise from Sigma-Delta Modulation (J. Candy & O. Benjamin). Multistage Sigma-Delta Modulation (W. Chou, et al.). Oversampled Sigma-Delta Modulation (R. Gray). Quantization Noise Spectra (R. Gray). Double-Loop Sigma-Delta Modulation with dc Input (N. He, et al.). A Unity Bit Coding Method by Negative Feedback (H. Inose & Y. Yasuda). Design of Stable High Order 1-Bit Sigma-Delta Modulators (T. Ritoniemi, et al.). Reduction of Quantizing Noise by Use of Feedback (H. Spang III & P. Schultheiss). Oversampled, Linear Predictive and Noise-Shaping Coders of Order N>1 (S. Tewksbury & R. Hallock). DESIGN, SIMULATION TECHNIQUES, AND ARCHITECTURES FOR OVERSAMPLING ConverterS. Design Methodology for SIGMADELTAM (B. Agrawal & K. Shenoi). Table-Based Simulation of Delta-Sigma Modulators (R. Bishop, et al.). Simulating and Testing Oversampled Analog-to-Digital Converters (B. Boser, et al.). A Use if Double Integration in Sigma Delta Modulation (J. Candy). An Oversampling Analog-to-Digital Converter Topology for High-Resolution Signal Acquisition Systems (L. Carley). Digitally Corrected Multi-Bit SIGMADELTA Data Converters (T. Cataltepe, et al.). A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters (K. Chao, et al.). One Bit Higher Order Sigma-Delta A/D Converters (P. Ferguson, et al.). Optimization of a Sigma-Delta Modulator by the Use of a Slow ADC (A. Gosslau & A. Gottwald). Circuit and Technology Considerations for MOS Delta-Sigma A/D Converters (M. Hauser & R. Brodersen). Technology Scaling and Performance Limitations in Delta-Sigma Analog-Digital Converters (M. Hauser). Delta-Sigma A/Ds with Reduced Sensitivity to Op Amp Noise and Gain (P. Hurst & R. Levinson). Multibit Oversampled SIGMA-DELTA A/D Converter with Digital Error Correction (L. Larson, et al.). An Improved Sigma-Delta Modulator Architecture (T. Leslie & B. Singh). A 13 Bit ISDN-Band Oversampled ADC Using Two-Stage Third Order Noise Shaping (L. Longo & M. Copeland). A 16-Bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping (Y. Matsuya, et al.). Improved Signal-to-Noise Ratio Using Tri-Level Delta-Sigma Modulation (J. Paulos, et al.). A Second-Order High-Resolution Incremental A/D Converter with Offset and Charge Injection Compensation (J. Robert & P. Deval). Improved Double Integation Delta-Sigma Modulations for A to D and D to A Conversion (Y. Shoji & T. Suzuki). Oversampling A-to-D and D-to-A Converters with Multistage Noise Shaping Modulators (K. Uchimura, et al.). Architectures for High-Order Multibit SIGMADELTA Modulators (R. Walden, et al.). Constraints Analysis for Oversampling A-to-D Converter Structures on VLSI Implementation (A. Yukawa). IMPLEMENTATIONS AND APPLICATIONS OF OVERSAMPLING A/D ConverterS. Design and Implementation of an Audio 18-bit Analog-to-Digital Converter Using Oversampling Techniques (R. Adams). The Design of Sigma-Delta Modulation Analog-to-Digital Converters (B. Boser & B. Wooley). A Noise-Shaping Coder Topology for 15+ Bit Converters (L. Carley). A Dual-Channel Voice-Band PCM Codec Using SIGMADELTA Modulation Technique (V. Friedman, et al.). MOS ADC-Filter Combination That Does Not Require Precision Analog Components (M. Hauser, et al.). A Multistage Delta-Sigma Modulator without Double Integration Loop (T. Hayashi, et al.). An Oversampled Sigma-Delta A/D Converter Circuit Using Two-Stage Fourth Order Modulator (T. Karema, et al.). A 12-Bit Sigma-Delta Analog-to-Digital Converter with 15-MHz Clock Rate (R. Koch, et al.). Area-Efficient Multichannel Oversampled PCM Voice-Band Coder (B. Leung, et al.). An 18b Oversampling A/D Converter for Digital Audio (K. Matsumoto, et al.). A 14-Bit 80-kHz Sigma-Delta A/D Converter: Modeling, Design, and Performance Evaluation (S. Norsworthy, et al.). Fully Differential CMOS Sigma-Delta Modulator for High Performance Analog-to-Digital Conversion with 5 V Operating Voltage (T. Ritoniemi, et al.). A High-Resolution CMOS Sigma-Delta A/D Converter with 320 kHz Output Rate (M. Rebeschini, et al.). A CMOS Slope Adaptive Delta Modulator (J. Scott, et al.). Stereo 16-Bit Delta-Sigma A/D Converter for Digital Audio (D. Welland, et al.). DIGITAL FILTERS FOR OVERSAMPLING A/D ConverterS. Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator (J. Candy, et al.). A Voiceband Codec with Digital Filtering (J. Candy, et al.). Decimation for Sigma Delta Modulation (J. Candy). Multirate Filter Designs Using Comb Filters (S. Chu & C. Burrus). Interpolation and Decimation of Digital Signals--A Tutorial Review (R. Crochiere & L. Rabiner). Wave Digital Decimation Filters in Oversample A/D Converters (E. Dijkstra, et al.). A Design Methodology for Decimation Filters in Sigma Delta A/D Converters (E. Dijkstra, et al.). On the Use of Modulo Arithmetic Comb Filters in Sigma Delta Modulators (E. Dijkstra, et al.). Nine Digital Filters for Decimation and Interpolation (D. Goodman & M. Carey). A Novel Architecture Design for VLSI Implementation of an FIR Decimation Filter (H. Meleis & P. Fur). Efficient VLSI-realizable Decimators for Sigma-Delta Analog-to-Digital Converters (T. Saramaki & H. Tenhunen). THEORY AND IMPLEMENTATIONS OF OVERSAMPLING D/A ConverterS. Double Interpolation for Digital-to-Analog Conversion (J. Candy & A.-N. Huynh). A 16-Bit 4th Order Noise-Shaping D/A Converter (L. Carley & J. Kenney). A CMOS Stereo 16-Bit D/A Converter for Digital Audio (P. Naus, et al.). Author Index. Subject Index. Editor's Biographies.
