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Abstraction Level

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A.a. Jerraya – One of the best experts on this subject based on the ideXlab platform.

  • fast and accurate timed execution of high Level embedded software using hw sw interface simulation model
    Asia and South Pacific Design Automation Conference, 2004
    Co-Authors: A. Bouchhima, A.a. Jerraya
    Abstract:

    In this paper, we propose a methodology to perform early desidesign stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS Abstraction Level and a HW Platform described at an arbitrary Abstraction Level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early desidesign stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).

  • Fast and accurate timed execution of high Level embedded software using HW/SW interface simulation model
    , 2004
    Co-Authors: A. Bouchhima, S. Yoo, A.a. Jerraya
    Abstract:

    We propose a methodology to perform early desidesign stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS Abstraction Level and a HW platform described at an arbitrary Abstraction Level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early desidesign stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).

A. Bouchhima – One of the best experts on this subject based on the ideXlab platform.

  • fast and accurate timed execution of high Level embedded software using hw sw interface simulation model
    Asia and South Pacific Design Automation Conference, 2004
    Co-Authors: A. Bouchhima, A.a. Jerraya
    Abstract:

    In this paper, we propose a methodology to perform early design stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS Abstraction Level and a HW Platform described at an arbitrary Abstraction Level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early design stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).

  • Fast and accurate timed execution of high Level embedded software using HW/SW interface simulation model
    , 2004
    Co-Authors: A. Bouchhima, S. Yoo, A.a. Jerraya
    Abstract:

    We propose a methodology to perform early design stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS Abstraction Level and a HW platform described at an arbitrary Abstraction Level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early design stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).

Andreas Muehlberger – One of the best experts on this subject based on the ideXlab platform.

  • power consumption profile analysis for security attack simulation in smart cards at high Abstraction Level
    Embedded Software, 2005
    Co-Authors: Klaus Rothbart, U Neffe, C Steger, Reinhold Weiss, Edgar Rieger, Andreas Muehlberger
    Abstract:

    Smart cards are embedded systems which are used in an increasing number of secure applications. As they store and deal with confidential and secret data many attacks are performed on these cards to reveal this private information. Consequently, the security demands on smart cards are very high. It is mandatory to evaluate the security of the design but this is performed often very late in the design process or when the chip has already been manufactured. This paper presents a hierarchical security attack simulation flow for smart card designs where security attacks can be simulated in the processor specific model at transaction layer 1 in SystemC. Therefore, the power consumption profile is analyzed at this Level. Preliminary results show that this analysis at high Abstraction Level can be used to determine vulnerabilities of the system to security attacks. Moreover, points to insert software countermeasures can easily be identified.

  • EMSOFT – Power consumption profile analysis for security attack simulation in smart cards at high Abstraction Level
    Proceedings of the 5th ACM international conference on Embedded software – EMSOFT '05, 2005
    Co-Authors: Klaus Rothbart, U Neffe, C Steger, Reinhold Weiss, Edgar Rieger, Andreas Muehlberger
    Abstract:

    Smart cards are embedded systems which are used in an increasing number of secure applications. As they store and deal with confidential and secret data many attacks are performed on these cards to reveal this private information. Consequently, the security demands on smart cards are very high. It is mandatory to evaluate the security of the design but this is performed often very late in the design process or when the chip has already been manufactured. This paper presents a hierarchical security attack simulation flow for smart card designs where security attacks can be simulated in the processor specific model at transaction layer 1 in SystemC. Therefore, the power consumption profile is analyzed at this Level. Preliminary results show that this analysis at high Abstraction Level can be used to determine vulnerabilities of the system to security attacks. Moreover, points to insert software countermeasures can easily be identified.

Mohamed Benromdhane – One of the best experts on this subject based on the ideXlab platform.

  • extending the transaction Level modeling approach for fast communication architecture exploration
    Design Automation Conference, 2004
    Co-Authors: Sudeep Pasricha, Nikil Dutt, Mohamed Benromdhane
    Abstract:

    System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems. System designers typically use Bus Cycle Accurate (BCA) models written in high Level languages such as C/C++ to explore the communication desidesign space. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for reliable performance exploration but results in slow simulation speeds for complex designs, even when they are modeled using high Level languages. Recently there have been several efforts to use the Transaction Level Modeling (TLM) paradigm for improving simulation performance in BCA models. However these BCA models capture a lot of details that can be eliminated when exploring communication architectures.In this paper we extend the TLM approach and propose a new and faster transaction-based modeling Abstraction Level (CCATB) to explore the communication desidesign space. Our Abstraction Level bridges the gap between the TLM and BCA Levels, and yields an average performance speedup of 55 over BCA models. We demonstrate how fast and accurate exploration of tradeoffs is possible for high-performance shared bus architectures such as AMBA 2.0 and AMBA 3.0 (AXI) in industrial strength designs at the proposed Abstraction Level.

Wolfgang Rosenstiel – One of the best experts on this subject based on the ideXlab platform.

  • A VHDL Reuse Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis
    Virtual Components Design and Reuse, 2001
    Co-Authors: Cordula Hansen, Oliver Bringmann, Wolfgang Rosenstiel
    Abstract:

    Due to the increasing complexity of digital systems, it is often desirable to start the design at higher Levels of Abstraction, e.g. at the algorithmic Level. The necessary transformations are then performed by commercial or scientific high-Level synthesis systems. In complex system design, the integration of user defined RT components (IP blocks) in the algorithmic specification is getting more and more important for the following reasons. First, several RT components appropriate for reuse may already exist. Second, the re-implementation of VHDL models emulating this behavior at the algorithmic Level is expensive and time-consuming. Third, some functional and timing behavior can only be implemented at the RT Level, e.g. interrupt handling, and interface components. Finally, several synthesis, simulation, and test environments which can be used for descriptions on different Abstraction Levels are already available. Therefore, this contribution addresses the problem of mixed Abstraction Level specifications for simulation and behavioral synthesis to allow the reuse of existing RT components.

  • An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design
    System-on-Chip Methodologies & Design Languages, 2001
    Co-Authors: Cordula Hansen, Oliver Bringmann, Wolfgang Rosenstiel
    Abstract:

    In complex system design, it is often desirable to start the system specification at higher Levels of Abstractions, e.g. at the algorithmic Level. The necessary refinements are then produced by commercial or academic high-Level synthesis systems. More and more often, the integration of user-defined RT components in the algorithmic specification plays an important role. First, some functional and timing behavior can only be implemented at the RT Level, e.g. interrupt handling, and interface components. Second, several RT components may already exist and are appropriate for reuse. Third, the re-implementation of VHDL models emulating this behavior at the algorithmic Level is expensive and time-consuming. Finally, several synthesis, simulation, and test environments exist which can be used for descriptions at different Abstraction Levels. Therefore, this paper addresses the problem of mixed Abstraction Level specifications for simulation and behavioral synthesis using object oriented component models. For this, the VHDL standard [IEEE93] without any extensions is used and the usual simulation and synthesis systems can be applied. The communication between algorithmic descriptions and VHDL components at the same or at lower Levels is executed using VHDL procedures. To reduce the design time required for the insertion of these procedures in the algorithmic specification, a preprocessor has been developed. The preprocessor allows the procedures to be applied without any extensive declarations of the corresponding RT components. The implementation of procedures emulating the component behavior at the algorithmic Level is also possible.

  • mixed Abstraction Level hardware synthesis from sdl for rapid prototyping
    Rapid System Prototyping, 1999
    Co-Authors: Oliver Bringmann, Wolfgang Rosenstiel, Annette Muth, Frank Slomka, Georg Farber, Richard Hofmann
    Abstract:

    SDL is currently gaining interest as a system Level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The investigations on the resource usage of SDL-to-VHDL designs presented in this paper identify two key challenges: minimizing the overhead introduced by SDL process infrastructure, and choosing the appropriate synthesis method. This paper presents a framework for SDL hardware synthesis where VHDL code generation, high-Level synthesis and RT-Level synthesis are combined. A configurable run-time environment implements services like data handling and message passing in efficient, hand-coded library components, which take into account properties of the target architecture. For these components RT-Level synthesis was found to be suitable. The behavior of each SDL process on the other hand is freely specified by the system designer. Depending on the type of application, i.e. complex data-oriented or control-oriented either high-Level synthesis, RT-Level synthesis, or a combination of both can prove to be optimal.