The Experts below are selected from a list of 15 Experts worldwide ranked by ideXlab platform
Tai-lun Li - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - Combined use of rising and falling Edge triggered Clocks for peak current reduction in IP-based SoC designs
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun LiAbstract:In a typical synchronous SoC design, a huge peak current often occurs near the time of an Active Clock Edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a Clock scheme of mixed rising and falling triggering Edges rather than one of pure rising (falling) triggering Edges. In this paper, we propose a Clock-triggering-Edge assignment technique and algorithms that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
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A peak current and power pad count reduction tool for system-level IC designers
2009 IEEE 13th International Symposium on Consumer Electronics, 2009Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun LiAbstract:In a typical synchronous circuit system, a large peak current occurs near the time of an Active Clock Edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a Clock scheme of mixed positive and negative triggering Edges rather than one of pure positive (negative) triggering Edges. In this paper, we propose a software tool that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each block of a given system-level design. The goal of the Clock-triggering-Edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.
Tsung-yi Wu - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - Combined use of rising and falling Edge triggered Clocks for peak current reduction in IP-based SoC designs
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun LiAbstract:In a typical synchronous SoC design, a huge peak current often occurs near the time of an Active Clock Edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a Clock scheme of mixed rising and falling triggering Edges rather than one of pure rising (falling) triggering Edges. In this paper, we propose a Clock-triggering-Edge assignment technique and algorithms that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
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A peak current and power pad count reduction tool for system-level IC designers
2009 IEEE 13th International Symposium on Consumer Electronics, 2009Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun LiAbstract:In a typical synchronous circuit system, a large peak current occurs near the time of an Active Clock Edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a Clock scheme of mixed positive and negative triggering Edges rather than one of pure positive (negative) triggering Edges. In this paper, we propose a software tool that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each block of a given system-level design. The goal of the Clock-triggering-Edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.
Shi-yi Huang - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - Combined use of rising and falling Edge triggered Clocks for peak current reduction in IP-based SoC designs
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun LiAbstract:In a typical synchronous SoC design, a huge peak current often occurs near the time of an Active Clock Edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a Clock scheme of mixed rising and falling triggering Edges rather than one of pure rising (falling) triggering Edges. In this paper, we propose a Clock-triggering-Edge assignment technique and algorithms that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.
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A peak current and power pad count reduction tool for system-level IC designers
2009 IEEE 13th International Symposium on Consumer Electronics, 2009Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun LiAbstract:In a typical synchronous circuit system, a large peak current occurs near the time of an Active Clock Edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a Clock scheme of mixed positive and negative triggering Edges rather than one of pure positive (negative) triggering Edges. In this paper, we propose a software tool that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each block of a given system-level design. The goal of the Clock-triggering-Edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.
Wayne Lu - One of the best experts on this subject based on the ideXlab platform.
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EXPERIENCING THE EFFECTS OF Clock TRANSITION TIMES ON ClockED STORAGE ELEMENTS
2015Co-Authors: Wayne LuAbstract:Designing synchronous sequential circuits consisting of Clocked storage elements such as flip-flops needs to observe stringent setup time and hold time constraints. If there is a timing violation, meaning the input data changes within the setup time and hold time window of the Active Clock Edge, the results of the Clocked storage elements could be unpredictable, a situation called metastable state. The cause and symptoms of metastable state are well established in the digital design literature. However, the effects of Clock transition times such as rise time and fall time on the behavior of a synchronous sequential circuit are rarely discussed. This paper presents an experiment to demonstrate that the transition time of a Clock signal can also affect the results of a Clocked storage element. Understanding this effect is crucial for designing more robust complex high-speed digital systems consisting of Clocked storage elements.
Alok Kumar Tripathi - One of the best experts on this subject based on the ideXlab platform.
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VDAT - Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop
Communications in Computer and Information Science, 2019Co-Authors: Muneeb Sulthan, Shubhajit Roy Chowdury, Rajnish Garg, Alok Kumar TripathiAbstract:The recent trend in minimizing power dissipation of digital integrated circuits through low power Clock storage has motivated the design of a conditional scan pulsed latch circuit. In this paper, a power efficient two bit conditional scan pulsed latch circuit as a solution For Master Slave Flip-Flop with a conditional pulse generator circuit has been proposed for the generation of Clock signal which will drive the scan latch circuit as the input Clock signal. This conditional pulse generation circuit will generate a pulse signal based on the mismatch between input data and the output data at the Active Clock Edge. With this scan pulsed latch circuit 65% power savings has been achieved when compared with traditional SCAN Master Slave Flip-Flop and 54% when compared with our own one bit conditional scan pulsed latch circuit designed using 28 nm FDSOI CMOS LVT technology.
