Active Clock Edge - Explore the Science & Experts | ideXlab

Scan Science and Technology

Contact Leading Edge Experts & Companies

Active Clock Edge

The Experts below are selected from a list of 15 Experts worldwide ranked by ideXlab platform

Tai-lun Li – 1st expert on this subject based on the ideXlab platform

  • ASP-DAC – Combined use of rising and falling Edge triggered Clocks for peak current reduction in IP-based SoC designs
    2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010
    Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun Li

    Abstract:

    In a typical synchronous SoC design, a huge peak current often occurs near the time of an Active Clock Edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a Clock scheme of mixed rising and falling triggering Edges rather than one of pure rising (falling) triggering Edges. In this paper, we propose a Clock-triggering-Edge assignment technique and algorithms that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

  • A peak current and power pad count reduction tool for system-level IC designers
    2009 IEEE 13th International Symposium on Consumer Electronics, 2009
    Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun Li

    Abstract:

    In a typical synchronous circuit system, a large peak current occurs near the time of an Active Clock Edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a Clock scheme of mixed positive and negative triggering Edges rather than one of pure positive (negative) triggering Edges. In this paper, we propose a software tool that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each block of a given system-level design. The goal of the Clock-triggering-Edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.

Tsung-yi Wu – 2nd expert on this subject based on the ideXlab platform

  • ASP-DAC – Combined use of rising and falling Edge triggered Clocks for peak current reduction in IP-based SoC designs
    2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010
    Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun Li

    Abstract:

    In a typical synchronous SoC design, a huge peak current often occurs near the time of an Active Clock Edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a Clock scheme of mixed rising and falling triggering Edges rather than one of pure rising (falling) triggering Edges. In this paper, we propose a Clock-triggering-Edge assignment technique and algorithms that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

  • A peak current and power pad count reduction tool for system-level IC designers
    2009 IEEE 13th International Symposium on Consumer Electronics, 2009
    Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun Li

    Abstract:

    In a typical synchronous circuit system, a large peak current occurs near the time of an Active Clock Edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a Clock scheme of mixed positive and negative triggering Edges rather than one of pure positive (negative) triggering Edges. In this paper, we propose a software tool that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each block of a given system-level design. The goal of the Clock-triggering-Edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.

Shi-yi Huang – 3rd expert on this subject based on the ideXlab platform

  • ASP-DAC – Combined use of rising and falling Edge triggered Clocks for peak current reduction in IP-based SoC designs
    2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010
    Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun Li

    Abstract:

    In a typical synchronous SoC design, a huge peak current often occurs near the time of an Active Clock Edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a Clock scheme of mixed rising and falling triggering Edges rather than one of pure rising (falling) triggering Edges. In this paper, we propose a Clock-triggering-Edge assignment technique and algorithms that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

  • A peak current and power pad count reduction tool for system-level IC designers
    2009 IEEE 13th International Symposium on Consumer Electronics, 2009
    Co-Authors: Tsung-yi Wu, Shi-yi Huang, Tai-lun Li

    Abstract:

    In a typical synchronous circuit system, a large peak current occurs near the time of an Active Clock Edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a Clock scheme of mixed positive and negative triggering Edges rather than one of pure positive (negative) triggering Edges. In this paper, we propose a software tool that can assign either a rising triggering Edge or a falling triggering Edge to each Clock of each block of a given system-level design. The goal of the Clock-triggering-Edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.