The Experts below are selected from a list of 765 Experts worldwide ranked by ideXlab platform
S M Reddy - One of the best experts on this subject based on the ideXlab platform.
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expanded definition of functional operation conditions and its effects on the computation of functional broadside tests
VLSI Test Symposium, 2008Co-Authors: I Pomeranz, S M ReddyAbstract:Functional operation of a Synchronous Sequential Circuit is defined to start after the Circuit is initialized to a known state, typically by a synchronizing sequence. The states that the Circuit can visit after it is synchronized are called reachable states, and functional operation consists of state-transitions between reachable states. We expand the definition of functional operation to include all the state-transitions that may be traversed during the application of the synchronizing sequence. This adds certain state-transitions that involve unreachable states to the definition of functional operation. Expanding the definition of functional operation is justified by the fact that the Circuit needs to be designed for correct operation during the synchronization process. It is advantageous when functional broadside tests are used to avoid over- testing. We study the effect of the expanded definition on the coverage of transition faults.
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primary input vectors to avoid in random test sequences for Synchronous Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: I Pomeranz, S M ReddyAbstract:Random test sequences may be used for manufacturing testing as well as for simulation-based design verification. This paper studies one of the reasons for the fact that random primary input sequences achieve very low fault coverage for Synchronous Sequential Circuits. It is shown that a Synchronous Sequential Circuit may have input cubes, or incompletely specified input vectors, that synchronize a subset of its state variables, i.e., it forces them to certain specified values. When an input cube c that synchronizes the subset of state variables S(c) has a small number of specified inputs, the input vectors covered by it may appear often in a random primary input sequence. As a result, the sequence will force the same values on the state variables in S(c) repeatedly. This may limit the fault coverage that the sequence can obtain. To address this issue, a procedure is described for modifying a random primary input sequence to eliminate the appearance of input vectors that synchronize subsets of state variables. It is demonstrated that this procedure has a significant effect on the fault coverage that can be achieved by random primary input sequences.
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vector restoration based static compaction using random initial omission
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004Co-Authors: I Pomeranz, S M ReddyAbstract:The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a Synchronous Sequential Circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted from the test sequence initially, to start the restoration process. We also propose a specific procedure for the initial omission process. Experimental results for a variety of Circuits and test sequences demonstrate that this procedure has a significant effect on the compacted test sequence length. Intuitively, the new procedure postpones the point at which the compaction procedure saturates, thus allowing smaller test lengths to be obtained before saturation is reached. The importance of continuing to explore this problem is related to the fact that static compaction procedures for Synchronous Sequential Circuits are important for scan Circuits as well.
A. Ghosh - One of the best experts on this subject based on the ideXlab platform.
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Retiming Sequential Circuits for low power
International Journal of High Speed Electronics and Systems, 1996Co-Authors: Jose Monteiro, Srinivas Devadas, A. GhoshAbstract:Switching activity is a primary cause of power dissipation in combinational and Sequential Circuits. In this paper, we present a retiming method that targets the power dissipation of a Sequential Circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a Synchronous Sequential Circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the Circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the Circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the Circuit. We give an exact method of estimating power in pipelined Sequential Circuits that accurately models the correlation between the vectors applied to the combinational logic of the Circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of Circuits.
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retiming Sequential Circuits for low power
International Conference on Computer Aided Design, 1993Co-Authors: Jose Monteiro, Srinivas Devadas, A. GhoshAbstract:Switching activity is the primary cause of power dissipation in CMOS combinational and Sequential Circuits. We give a method of estimating power in pipelined Sequential CMOS Circuits that accurately models the correlation between the vectors applied to the combinational logic of the Circuit. We explore the implications of the observation that the switching activity at flip-flop outputs in a Synchronous Sequential Circuit can be significantly less than the activity at the flip-flop inputs. We present a retiming method that targets the power dissipation of a Sequential Circuit.
I Pomeranz - One of the best experts on this subject based on the ideXlab platform.
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expanded definition of functional operation conditions and its effects on the computation of functional broadside tests
VLSI Test Symposium, 2008Co-Authors: I Pomeranz, S M ReddyAbstract:Functional operation of a Synchronous Sequential Circuit is defined to start after the Circuit is initialized to a known state, typically by a synchronizing sequence. The states that the Circuit can visit after it is synchronized are called reachable states, and functional operation consists of state-transitions between reachable states. We expand the definition of functional operation to include all the state-transitions that may be traversed during the application of the synchronizing sequence. This adds certain state-transitions that involve unreachable states to the definition of functional operation. Expanding the definition of functional operation is justified by the fact that the Circuit needs to be designed for correct operation during the synchronization process. It is advantageous when functional broadside tests are used to avoid over- testing. We study the effect of the expanded definition on the coverage of transition faults.
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primary input vectors to avoid in random test sequences for Synchronous Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: I Pomeranz, S M ReddyAbstract:Random test sequences may be used for manufacturing testing as well as for simulation-based design verification. This paper studies one of the reasons for the fact that random primary input sequences achieve very low fault coverage for Synchronous Sequential Circuits. It is shown that a Synchronous Sequential Circuit may have input cubes, or incompletely specified input vectors, that synchronize a subset of its state variables, i.e., it forces them to certain specified values. When an input cube c that synchronizes the subset of state variables S(c) has a small number of specified inputs, the input vectors covered by it may appear often in a random primary input sequence. As a result, the sequence will force the same values on the state variables in S(c) repeatedly. This may limit the fault coverage that the sequence can obtain. To address this issue, a procedure is described for modifying a random primary input sequence to eliminate the appearance of input vectors that synchronize subsets of state variables. It is demonstrated that this procedure has a significant effect on the fault coverage that can be achieved by random primary input sequences.
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vector restoration based static compaction using random initial omission
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004Co-Authors: I Pomeranz, S M ReddyAbstract:The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a Synchronous Sequential Circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted from the test sequence initially, to start the restoration process. We also propose a specific procedure for the initial omission process. Experimental results for a variety of Circuits and test sequences demonstrate that this procedure has a significant effect on the compacted test sequence length. Intuitively, the new procedure postpones the point at which the compaction procedure saturates, thus allowing smaller test lengths to be obtained before saturation is reached. The importance of continuing to explore this problem is related to the fact that static compaction procedures for Synchronous Sequential Circuits are important for scan Circuits as well.
David L Foster - One of the best experts on this subject based on the ideXlab platform.
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an undergraduate survey course on aSynchronous Sequential logic ladder logic and fuzzy logic
IEEE Transactions on Education, 2012Co-Authors: David L FosterAbstract:For a basic foundation in computer engineering, universities traditionally teach Synchronous Sequential Circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like Kettering University, Flint, MI, students could strongly benefit from a more diverse set of topics and tool experience in their curriculum. This paper presents an undergraduate course that includes introductions to Sequential Circuit design using aSynchronous logic, ladder logic and its general implementation on programmable logic controllers, and fuzzy logic targeted at both PC and embedded processor applications. The paper discusses the structure of the course, the objectives and material, the laboratory platforms, and the evaluations of the first course offerings that show the course's success.
A Matrosova - One of the best experts on this subject based on the ideXlab platform.
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a fault tolerant Sequential Circuit design for soft errors based on fault secure Circuit
East-West Design and Test Symposium, 2016Co-Authors: S Ostanin, A Matrosova, N Butorina, V LavrovAbstract:This paper presents a fault-tolerant Synchronous Sequential Circuit design based on fault-secure system with low overhead. The scheme has only one fault-secure Sequential Circuit, a normal (unprotected) Sequential Circuit, a checker and rather simple XOR Circuit. It is proved the reliability properties of the suggested scheme not only for single stuck-at faults at gate poles but for path delay faults transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared.
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a fault tolerant Sequential Circuit design for safs and pdfs soft errors
International On-Line Testing Symposium, 2016Co-Authors: A Matrosova, S Ostanin, I Kirienko, E NikolaevaAbstract:This paper presents a fault-tolerant Synchronous Sequential Circuit design based on self-checking system with low overhead. The scheme has a self-checking Sequential Circuit, a not self-testing checker and a normal (unprotected) Sequential Circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.
