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Tanay Chattopadhyay – One of the best experts on this subject based on the ideXlab platform.

  • Design of all optical ternary logic based half Adder Circuit and it’s applications
    Journal of Optics, 2015
    Co-Authors: Panchatapa Bhowmik, Tanay Chattopadhyay

    Abstract:

    Ternary Half Adder Circuit with optical nonlinear material (OPNLM) based switch is proposed and discussed. The designing of Ternary incrementer / decrementer Circuits and Ternary full Adder Circuit with the proposed Ternary half Adder Circuit are also described here. Polarized lights of different states are considered as the inputs of the logical operations.

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  • designing of optimized all optical half Adder Circuit using single quantum dot semiconductor optical amplifier assisted mach zehnder interferometer
    Journal of Lightwave Technology, 2013
    Co-Authors: Dilip Kumar Gayen, Tanay Chattopadhyay

    Abstract:

    A new and novel scheme for a high speed all-optical half Adder based on single Quantum-dot semiconductor optical amplifier (QD-SOA) assisted Mach-Zehnder interferometer (MZI) is theoretically investigated and discussed. In this proposed scheme, pair of input data streams are simultaneously drive the switch to produce sum and carry. In this new design, only single switch can be utilized to design half Adder Circuit and no additional input beam is required other than two input signals. This design is simpler, smaller and compact than our previously proposed design . The impact of the peak data power as well as of the QD-SOAs current density and maximum modal gain on the ER, Q factor with current densities and electron relaxation times etc are explored and assessed by means of numerical simulations.

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  • quaternary galois field Adder based all optical multivalued logic Circuits
    Applied Optics, 2009
    Co-Authors: Tanay Chattopadhyay, Chinmoy Taraphdar, Jitendra Nath Roy

    Abstract:

    Galois field (GF) algebraic expressions have been found to be promising choices for reversible and quantum implementation of multivalued logic. For the first time to our knowledge, we developed GF(4) Adder multivalued (four valued) logic Circuits in an all-optical domain. The principle and possibilities of an all-optical GF(4) Adder Circuit are described. The theoretical model is presented and verified through numerical simulation. The quaternary inverter, successor, clockwise cycle, and counterclockwise cycle gates are proposed with the help of the all-optical GF(4) Adder Circuit. In this scheme different quaternary logical states are represented by different polarized light. A terahertz optical asymmetric demultiplexer interferometric switch plays an important role in this scheme.

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Ahsan Raja Chowdhury – One of the best experts on this subject based on the ideXlab platform.

  • Design of a compact reversible binary coded decimal Adder Circuit
    Journal of Systems Architecture, 2006
    Co-Authors: Hafiz Md Hasan Babu, Ahsan Raja Chowdhury

    Abstract:

    Reversible logic is an emerging research area and getting remarkable interests over the past few years. Interest is sparked in reversible logic by its applications in several technologies, such as quantum, optical, thermodynamics and adiabatic CMOS. This paper represents a synthesis method to realize reversible binary coded decimal Adder Circuit. Firstly, a reversible full-Adder Circuit has been proposed that shows the improvement over the two existing Circuits. A lower bound is also proposed for the reversible full-Adder Circuit on the number of garbage outputs (bits needed for reversibility, but not required for the output of the Circuit). After that, a final improvement is presented for the reversible full-Adder Circuit. Finally, a new reversible Circuit has been proposed, namely reversible binary coded decimal (BCD) Adder, which is the first ever proposed in reversible logic synthesis. In the way to propose reversible BCD Adder, a reversible n-bits parallel Adder Circuit is also shown. Lower bounds for the reversible BCD Adder in terms of number of garbage outputs and number of reversible gates are also shown. Delay has also been calculated for each Circuit.

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  • synthesis of full Adder Circuit using reversible logic
    International Conference on VLSI Design, 2004
    Co-Authors: Hafiz Md Hasan Babu, Syed Mostahed Ali Chowdhury, M R Islam, Ahsan Raja Chowdhury

    Abstract:

    A reversible gate has the equal number of inputs and outputs and one-to-one mappings between input vectors and output vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states. This correspondence introduces a reversible full-Adder Circuit that requires only three reversible gates and produces least number of “garbage outputs “, that is two. After that, a theorem has been proposed that proves the optimality of the propounded Circuit in terms of number of garbage outputs. An efficient algorithm is also introduced in this paper that leads to construct a reversible Circuit.

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  • reversible logic synthesis for minimization of full Adder Circuit
    Digital Systems Design, 2003
    Co-Authors: Hafiz Md Hasan Babu, Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury

    Abstract:

    Reversible logic is of the growing importance to many future technologies. A reversible Circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the “garbage bit” and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-Adder Circuit contains only three gates and two garbage outputs whereas earlier full-Adder Circuit by M. Perkowski et al. (2001) requires four gates and produces two garbage outputs and another existing full-Adder Circuit by Md. H. H Azad Khan (2002) requires three gates but produces three garbage outputs. Thus, the proposed full-Adder Circuit is efficient in terms of number of gates with compared to M. Perkowski et al. (2001) as well as in terms of number of garbage outputs with compared to Md. H. H Azad Khan (2002).

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Hafiz Md Hasan Babu – One of the best experts on this subject based on the ideXlab platform.

  • Design of a compact reversible binary coded decimal Adder Circuit
    Journal of Systems Architecture, 2006
    Co-Authors: Hafiz Md Hasan Babu, Ahsan Raja Chowdhury

    Abstract:

    Reversible logic is an emerging research area and getting remarkable interests over the past few years. Interest is sparked in reversible logic by its applications in several technologies, such as quantum, optical, thermodynamics and adiabatic CMOS. This paper represents a synthesis method to realize reversible binary coded decimal Adder Circuit. Firstly, a reversible full-Adder Circuit has been proposed that shows the improvement over the two existing Circuits. A lower bound is also proposed for the reversible full-Adder Circuit on the number of garbage outputs (bits needed for reversibility, but not required for the output of the Circuit). After that, a final improvement is presented for the reversible full-Adder Circuit. Finally, a new reversible Circuit has been proposed, namely reversible binary coded decimal (BCD) Adder, which is the first ever proposed in reversible logic synthesis. In the way to propose reversible BCD Adder, a reversible n-bits parallel Adder Circuit is also shown. Lower bounds for the reversible BCD Adder in terms of number of garbage outputs and number of reversible gates are also shown. Delay has also been calculated for each Circuit.

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  • synthesis of full Adder Circuit using reversible logic
    International Conference on VLSI Design, 2004
    Co-Authors: Hafiz Md Hasan Babu, Syed Mostahed Ali Chowdhury, M R Islam, Ahsan Raja Chowdhury

    Abstract:

    A reversible gate has the equal number of inputs and outputs and one-to-one mappings between input vectors and output vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states. This correspondence introduces a reversible full-Adder Circuit that requires only three reversible gates and produces least number of “garbage outputs “, that is two. After that, a theorem has been proposed that proves the optimality of the propounded Circuit in terms of number of garbage outputs. An efficient algorithm is also introduced in this paper that leads to construct a reversible Circuit.

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  • reversible logic synthesis for minimization of full Adder Circuit
    Digital Systems Design, 2003
    Co-Authors: Hafiz Md Hasan Babu, Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury

    Abstract:

    Reversible logic is of the growing importance to many future technologies. A reversible Circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the “garbage bit” and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-Adder Circuit contains only three gates and two garbage outputs whereas earlier full-Adder Circuit by M. Perkowski et al. (2001) requires four gates and produces two garbage outputs and another existing full-Adder Circuit by Md. H. H Azad Khan (2002) requires three gates but produces three garbage outputs. Thus, the proposed full-Adder Circuit is efficient in terms of number of gates with compared to M. Perkowski et al. (2001) as well as in terms of number of garbage outputs with compared to Md. H. H Azad Khan (2002).

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