The Experts below are selected from a list of 28935 Experts worldwide ranked by ideXlab platform
Marek Perkowski - One of the best experts on this subject based on the ideXlab platform.
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quantum Logic Synthesis by symbolic reachability analysis
Design Automation Conference, 2004Co-Authors: William N N Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek PerkowskiAbstract:Reversible quantum Logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability analysis where the primary inputs are purely binary. we use symbolic reachability analysis, a technique most commonly used in model checking (a way of formal verification), to synthesize the optimum quantum circuits. We present an exact Synthesis method with optimal quantum cost and a speedup method with non-optimal quantum cost. Both our methods guarantee the synthesizeability of all reversible circuits. Unlike previous works which use permutative reversible gates, we use a lower level library which includes non-permutative quantum gates. For the first time, problems in quantum Logic Synthesis have been reduced to those of multiple-valued Logic Synthesis thus reducing the search space and algorithm complexity. We synthesized quantum circuits for gate, half-adder, full-adder, etc. with the smallest cost.. Our approach obtains the minimum cost quantum circuits for Miller's gate, half-adder, and full-adder, which are better than previous results. In addition, we prove the minimum quantum cost (using our elementary quantum gates) for Fredkin, Peres, and Toffoli gates. Our work constitutes the first successful experience of applying satisfiability with formal methods to quantum Logic Synthesis.
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Logic Synthesis of reversible wave cascades
IWLS, 2002Co-Authors: Alan Mishchenko, Marek PerkowskiAbstract:A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible Logic Synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible Logic Synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible Synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks.
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IWLS - Logic Synthesis of Reversible Wave Cascades
2002Co-Authors: Alan Mishchenko, Marek PerkowskiAbstract:A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible Logic Synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible Logic Synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible Synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks.
Alan Mishchenko - One of the best experts on this subject based on the ideXlab platform.
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lazy man s Logic Synthesis
International Conference on Computer Aided Design, 2012Co-Authors: Wenlong Yang, Lingli Wang, Alan MishchenkoAbstract:Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by Logic Synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy" approach to Logic Synthesis based on the following observations: (a) optimal or near-optimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a case-study shows that Logic level minimization using lazy man's Synthesis improves delay after LUT mapping into 4- and 6-input LUTs, compared to earlier work on high-effort delay optimization.
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ICCAD - Lazy man's Logic Synthesis
Proceedings of the International Conference on Computer-Aided Design - ICCAD '12, 2012Co-Authors: Wenlong Yang, Lingli Wang, Alan MishchenkoAbstract:Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by Logic Synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy" approach to Logic Synthesis based on the following observations: (a) optimal or near-optimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a case-study shows that Logic level minimization using lazy man's Synthesis improves delay after LUT mapping into 4- and 6-input LUTs, compared to earlier work on high-effort delay optimization.
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Scalable Logic Synthesis using a Simple Circuit Structure
2006Co-Authors: Alan Mishchenko, Robert K. BraytonAbstract:This paper proposes an alternate approach to Logic Synthesis using rewriting and peephole optimization but from a modern perspective. We use a simple Logic structure (AIGs) as the basis for all the algorithms, and rely on efficient techniques, such as precomputation, reconvergence analysis, cut enumeration, Boolean matching, exhaustive simulation of small Logic cones, and local resource-aware decision procedures based on Boolean satisfiability. The result is a Logic Synthesis flow that is orders of magnitude faster than traditional ones and more scalable, being applicable to large industrial netlists with millions of gates.
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IWLS - A Boolean Paradigm in Multi-Valued Logic Synthesis.
2002Co-Authors: Alan Mishchenko, Robert K. BraytonAbstract:Optimization algorithms used in binary multi-level Logic Synthesis, such as network simplification, Logic extraction, and resubstitution, have been treated independently and did not share computational procedures. Using multi-valued Logic Synthesis, some common conceptual and computational cores underlying these algorithms can be identified. We present an overview of a Boolean paradigm in multivalued Logic Synthesis. The Boolean algorithms are generalizations of the usual ones and can replace these and the traditional algebraic algorithms, offering improved trade-offs between computation speed and optimization quality.
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Logic Synthesis of reversible wave cascades
IWLS, 2002Co-Authors: Alan Mishchenko, Marek PerkowskiAbstract:A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible Logic Synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible Logic Synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible Synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks.
Giovanni De Micheli - One of the best experts on this subject based on the ideXlab platform.
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Logic Synthesis for Established and Emerging Computing
Proceedings of the IEEE, 2019Co-Authors: Eleonora Testa, Mathias Soeken, Luca Gaetano Amar, Giovanni De MicheliAbstract:Logic Synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of Synthesis problems has shown to be very useful toward both attempting to solve some Logic problems exactly—which is computationally possible for instances of limited size today—as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technoLogical advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific Synthesis flows to assess feasibility and scalability. This review highlights recent progress in Logic Synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported.
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LUT-Based Hierarchical Reversible Logic Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019Co-Authors: Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De MicheliAbstract:We present a Synthesis framework to map Logic networks into quantum circuits for quantum computing. The Synthesis framework is based on lookup-table (LUT) networks, which play a key role in conventional Logic Synthesis. Establishing a connection between LUTs in an LUT network and reversible single-target gates in a reversible network allows us to bridge conventional Logic Synthesis with Logic Synthesis for quantum computing, despite several fundamental differences. We call our Synthesis framework LUT-based hierarchical reversible Logic Synthesis (LHRS). Input to LHRS is a classical Logic network representing an arbitrary Boolean combinational operation; output is a quantum network (realized in terms of Clifford+ T gates). The framework allows one to account for qubit count requirements imposed by the overlying quantum algorithm or target quantum computing hardware. In a fast first step, an initial network is derived that only consists of single-target gates and already completely determines the number of qubits in the final quantum network. Different methods are then used to map each single-target gate into Clifford+ T gates, while aiming at optimally using available resources. We demonstrate the versatility of our method by conducting a design space exploration using different parameters on a set of large combinational benchmarks. On the same benchmarks, we show that our approach can advance over the state-of-the-art hierarchical reversible Logic Synthesis algorithms.
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Exploratory Logic Synthesis for multiple independent gate FETs
Functionality-Enhanced Devices An alternative to Moore's Law, 2018Co-Authors: Luca Amarù, Pierre-emmanuel Gaillardon, Subhasish Mitra, Giovanni De MicheliAbstract:The use of multiple independent gate field effect transistors (MIGFETs) is a promising scaling path for digital electronics. While a MIGFET functionality increases with the number of gates, also its physical implementation cost grows. In this book chapter, the authors address this question from a Logic Synthesis standpoint. The aim is to determine whether or not an increasing number of gates leads to more compact design implementations. They propose a Logic Synthesis methodology that exploits at a fine grain a switching function for a target MIGFET, potentially being any Boolean function. By using device and interconnect models, they estimate the characteristics of the synthesized circuits.
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Majority Logic Synthesis
2018Co-Authors: Luca Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias SoekenAbstract:The majority function ⟨xyz⟩ evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in Logic Synthesis applications for many decades. Knuth refers to the majority function in the last volume of his seminal The Art of Computer Programming as "probably the most important ternary operation in the entire universe. " Majority Logic sythesis has recently regained signficant interest in the design automation community due to nanoemerging technologies which operate based on the majority function. In addition , majority Logic Synthesis has successfully been employed in CMOS-based applications such as standard cell or FPGA mapping. This tutorial gives a broad introduction into the field of majority Logic Synthesis. It will review fundamental results and describe recent contributions from theory, practice, and applications.
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The EPFL Logic Synthesis Libraries.
arXiv: Logic in Computer Science, 2018Co-Authors: Mathias Soeken, Heinz Riener, Winston Haaswijk, Giovanni De MicheliAbstract:We present a collection of modular open source C++ libraries for the development of Logic Synthesis applications. The alice library is a lightweight wrapper for shell interfaces, which is the typical user interface for most Logic Synthesis and design automation applications. It includes a Python interface to support scripting. The lorina library is a parsing library for simple file formats commonly used in Logic Synthesis. It includes several customizable parsing algorithms and a flexible diagnostic engine. The kitty library is a truth table library for explicit representation and manipulation of Boolean functions. It requires less overhead compared to symbolic counterparts such as binary decision diagrams, but is limited by the number of variables of the Boolean function to represent. Finally, percy is an exact Synthesis library with multiple engines to find optimum Logic networks. All libraries are well documented and well tested. Furthermore, being header-only, the libraries can be readily used as core components in complex Logic Synthesis systems.
Alberto Sangiovanni-vincentelli - One of the best experts on this subject based on the ideXlab platform.
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DAC - Are Logic Synthesis tools robust
Proceedings of the 48th Design Automation Conference on - DAC '11, 2011Co-Authors: Alberto Puggelli, Tobias Welp, Andreas Kuehlmann, Alberto Sangiovanni-vincentelliAbstract:A systematic investigation is presented about the robustness of Logic Synthesis tools to equivalence-preserving transformations of the input Verilog file. We have developed a framework that: 1) parses Verilog behavioral models into an abstract syntax tree; 2) generates random equivalence-preserving transformations on the syntax tree, and; 3) writes the transformed design back in Verilog format. The original and the transformed Verilog descriptions are then checked for equivalence and synthesized. Results show that average (peak) improvements in area of 2.5% (11%) and length of the critical path of 4% (13%) are achievable. Indeed these figures are comparable to recent advancements in Logic Synthesis ([17] [8] achieve 4.9% (23%) 5% (24%) improvements area-wise, respectively), signaling a relevant lack of robustness in Synthesis tools. This lack of robustness suggests that new Synthesis algorithms should be evaluated by measuring the average improvement on several transformed files to assess their real contributions to the quality of the results.
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Logic Synthesis for manufacturability
IEEE Design and Test of Computers, 2004Co-Authors: Alessandra Nardi, Alberto Sangiovanni-vincentelliAbstract:Design optimization during Synthesis is for area and/or performance while optimization for yield occurs at the layout level. To obtain abstraction level for yield optimization by introducing an interesting approach to yield-driven Logic Synthesis. Design for manufacturability denotes all techniques designers use to estimate and control yield and robustness during the design phase, prior to manufacturing.
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ICCAD - Wireplanning in Logic Synthesis
Proceedings of the 1998 IEEE ACM international conference on Computer-aided design - ICCAD '98, 1998Co-Authors: Wilsin Gosti, Robert K. Brayton, Amit Narayan, Alberto Sangiovanni-vincentelliAbstract:In this paper, we propose a new Logic Synthesis methodology to deal with the increasing importance of the interconnect delay in deep submicron technologies. We first show that conventional Logic Synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose Logic Synthesis techniques which produce circuits which are "better" for placement. Our proposed approach still separates Logic Synthesis from physical design.
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Multilevel Logic Synthesis
Proceedings of the IEEE, 1990Co-Authors: Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni-vincentelliAbstract:A survey of Logic Synthesis techniques for multilevel combinational Logic is presented. The goal is to provide more in-depth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis of the Synthesis methods that have become established as practically significant are provided. Also included are some methods that have theoretical interest and potential for future impact. The discussion covers notation and definitions, representation of the network and nodes, Logic decomposition/restructuring, Logic optimization/minimization, Logic Synthesis and testing, and technology mapping
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ITC - Optimal Logic Synthesis and testability: two faces of the same coin
International Test Conference 1988 Proceeding@m_New Frontiers in Testing, 1Co-Authors: Srinivas Devadas, A.r. Newton, Alberto Sangiovanni-vincentelliAbstract:The relationships between test generation and Logic minimization are described. An overview of the state of the art in combinational and sequential Logic Synthesis is provided. Combinational Logic Synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination Logic can be obtained as a by-product of the Logic minimization step. Equally intimate relationships between the problems of sequential Logic Synthesis and sequential test generation are envisioned. A recently developed Synthesis technique of constrained state assignment and Logic optimization which ensures fully testable sequential machines is described briefly. >
Robert K. Brayton - One of the best experts on this subject based on the ideXlab platform.
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Scalable Logic Synthesis using a Simple Circuit Structure
2006Co-Authors: Alan Mishchenko, Robert K. BraytonAbstract:This paper proposes an alternate approach to Logic Synthesis using rewriting and peephole optimization but from a modern perspective. We use a simple Logic structure (AIGs) as the basis for all the algorithms, and rely on efficient techniques, such as precomputation, reconvergence analysis, cut enumeration, Boolean matching, exhaustive simulation of small Logic cones, and local resource-aware decision procedures based on Boolean satisfiability. The result is a Logic Synthesis flow that is orders of magnitude faster than traditional ones and more scalable, being applicable to large industrial netlists with millions of gates.
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Logic Synthesis Overview
The Best of ICCAD, 2003Co-Authors: Robert K. Brayton, John A. DarringerAbstract:The dream of generating efficient Logic implementations from higher level specifications originated with the works of Boole,[57] Shannon [58], Quine and McCluskey[35, 36]. Interest in Logic Synthesis grew during the 60’s and 70’s, as the computers being designed became more complex. Although many theoretical advances were made, the first examples of practical Synthesis did not occur until the later 70’s. Programmable Logic arrays, PLAs, were minimized with the program, MINI, [15] and used on many product chips in IBM. LSS[10, 9] was the first example of production Synthesis of gate array chips. It was based on local transformations and compiler techniques for optimizing Logic, mapping gates to a specific technology. It was used on hundreds of product chips in IBM and was rewritten later with many significant refinements as BooleDozer[11]. These optimization methods were also used in the first offerings from Synop-sys[12, 13], a company formed in 1986 (originally Optimal Solutions) to market Synthesis technology developed at General Electric. Synopsys succeeded in bringing Synthesis to the commercial market enabling a dramatic advance in design productivity. The years that followed saw many important developments that produced improvements in execution speed, quality of results and ability to deal with real technologies. Today, Logic Synthesis is a critical part of almost all chip development projects.
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IWLS - A Boolean Paradigm in Multi-Valued Logic Synthesis.
2002Co-Authors: Alan Mishchenko, Robert K. BraytonAbstract:Optimization algorithms used in binary multi-level Logic Synthesis, such as network simplification, Logic extraction, and resubstitution, have been treated independently and did not share computational procedures. Using multi-valued Logic Synthesis, some common conceptual and computational cores underlying these algorithms can be identified. We present an overview of a Boolean paradigm in multivalued Logic Synthesis. The Boolean algorithms are generalizations of the usual ones and can replace these and the traditional algebraic algorithms, offering improved trade-offs between computation speed and optimization quality.
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ICCAD - Wireplanning in Logic Synthesis
Proceedings of the 1998 IEEE ACM international conference on Computer-aided design - ICCAD '98, 1998Co-Authors: Wilsin Gosti, Robert K. Brayton, Amit Narayan, Alberto Sangiovanni-vincentelliAbstract:In this paper, we propose a new Logic Synthesis methodology to deal with the increasing importance of the interconnect delay in deep submicron technologies. We first show that conventional Logic Synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose Logic Synthesis techniques which produce circuits which are "better" for placement. Our proposed approach still separates Logic Synthesis from physical design.
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Multilevel Logic Synthesis
Proceedings of the IEEE, 1990Co-Authors: Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni-vincentelliAbstract:A survey of Logic Synthesis techniques for multilevel combinational Logic is presented. The goal is to provide more in-depth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis of the Synthesis methods that have become established as practically significant are provided. Also included are some methods that have theoretical interest and potential for future impact. The discussion covers notation and definitions, representation of the network and nodes, Logic decomposition/restructuring, Logic optimization/minimization, Logic Synthesis and testing, and technology mapping
