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Earl E. Swartzlander - One of the best experts on this subject based on the ideXlab platform.

  • Floating-Point Fused Multiply-Add Architectures
    2007 Conference Record of the Forty-First Asilomar Conference on Signals Systems and Computers, 2007
    Co-Authors: Quinnell Eric C, Earl E. Swartzlander, C. Lemonds
    Abstract:

    Two new floating-point fused multiply-add architectures for the single instruction execution of (A times B) + C are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as a collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the advanced micro devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.

  • A Spanning Tree Carry Lookahead Adder
    IEEE Transactions on Computers, 1992
    Co-Authors: Thomas W. Lynch, Earl E. Swartzlander
    Abstract:

    The design of the 56-b significant adder used in the advanced micro devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums...

  • A spanning tree carry lookahead adder
    IEEE Transactions on Computers, 1992
    Co-Authors: Thomas W. Lynch, Earl E. Swartzlander
    Abstract:

    The design of the 56-b significant adder used in the advanced micro devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >

  • IEEE Symposium on Computer Arithmetic - The redundant cell adder
    [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic, 1
    Co-Authors: Thomas W. Lynch, Earl E. Swartzlander
    Abstract:

    The design of the 56-b significand adder for the advanced micro devices, Am29050 microprocessor, is described. This is a 1- mu m design rule CMOS realization of a high-performance RISC (reduced instruction set computer) microprocessor that implements IEEE Standard 754 floating-point arithmetic. To achieve an add time of under 4 ns for the 56-b significand and to avoid multistage pipelines which significantly impair compiler efficiency, a redundant cell adder has been developed. This redundant cell adder design combines carry lookahead adders realized with Manchester carry chains and the carry select adder concept to achieve approximately twice the speed of the traditional carry lookahead adder. This adder achieves a 3.2-ns measured add time for 56-bit operands and is of reasonable size. >

Thomas W. Lynch - One of the best experts on this subject based on the ideXlab platform.

  • A Spanning Tree Carry Lookahead Adder
    IEEE Transactions on Computers, 1992
    Co-Authors: Thomas W. Lynch, Earl E. Swartzlander
    Abstract:

    The design of the 56-b significant adder used in the advanced micro devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums...

  • A spanning tree carry lookahead adder
    IEEE Transactions on Computers, 1992
    Co-Authors: Thomas W. Lynch, Earl E. Swartzlander
    Abstract:

    The design of the 56-b significant adder used in the advanced micro devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >

  • IEEE Symposium on Computer Arithmetic - The redundant cell adder
    [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic, 1
    Co-Authors: Thomas W. Lynch, Earl E. Swartzlander
    Abstract:

    The design of the 56-b significand adder for the advanced micro devices, Am29050 microprocessor, is described. This is a 1- mu m design rule CMOS realization of a high-performance RISC (reduced instruction set computer) microprocessor that implements IEEE Standard 754 floating-point arithmetic. To achieve an add time of under 4 ns for the 56-b significand and to avoid multistage pipelines which significantly impair compiler efficiency, a redundant cell adder has been developed. This redundant cell adder design combines carry lookahead adders realized with Manchester carry chains and the carry select adder concept to achieve approximately twice the speed of the traditional carry lookahead adder. This adder achieves a 3.2-ns measured add time for 56-bit operands and is of reasonable size. >

L.p. Deshmukh - One of the best experts on this subject based on the ideXlab platform.

  • Quaternary Co1−x−yZnxCdyS thin films: A facile synthesis approach and its aptness for the applications in micro-devices
    Materials Letters, 2016
    Co-Authors: S.s. Kamble, Andrzej Sikora, S. L. Deshmukh, G.t. Chavan, V.s. Karande, S.t. Pawar, N.l. Tarwal, L.p. Deshmukh
    Abstract:

    Abstract The synthesis of multicomponent semiconducting thin films has become the subject of intensive research. The development of deposition-characterization techniques and property correlation and understanding of these materials are critical for the successful implementation of a whole new generation of advanced micro-devices. A wide range of discussion made in this article include facile chemical synthesis of Zn, Cd(CoS) thin films and characterization pertaining to the studies on compositional, morphological, optical and electrical transport aspects. The overall discussion involved herein will be useful to establish further engrossment of the researchers in the mentioned quaternary system.

T. Y. Tseng - One of the best experts on this subject based on the ideXlab platform.

  • Preparation and properties of tantalum pentoxide (Ta_2O_5) thin films for ultra large scale integrated circuits (ULSIs) application – A review
    Journal of Materials Science: Materials in Electronics, 1999
    Co-Authors: S. Ezhilvalavan, T. Y. Tseng
    Abstract:

    Tantalum pentoxide (Ta_2O_5) thin films have rapidly evolved into an important field of research/development for both basic and applied science with the promise of creating a new generation of advanced micro devices for electronics applications. This paper provides a broad review of the current status and future trends of _Ta2O_5 thin films as a highly promising storage dielectric material for high-density dynamic random access memory applications. Various methods of thin film material processing are briefly reviewed. The physical, electrical and dielectric characteristics of Ta_2O_5 thin films with specific examples from recent literature and the associated conduction mechanisms are summarized and discussed. Some suggestions to improve the electrical properties of the films are finally included. ©1998Kluwer Academic Publishers

  • Preparation and properties of tantalum pentoxide (Ta2O5) thin films for ultra large scale integrated circuits (ULSIs) application - A review
    Journal of Materials Science: Materials in Electronics, 1999
    Co-Authors: S. Ezhilvalavan, T. Y. Tseng
    Abstract:

    Tantalum pentoxide (Ta2O5) thin films have rapidly evolved into an important field of research/development for both basic and applied science with the promise of creating a new generation of advanced micro devices for electronics applications. This paper provides a broad review of the current status and future trends of Ta2O5 thin films as a highly promising storage dielectric material for high-density dynamic random access memory applications. Various methods of thin film material processing are briefly reviewed. The physical, electrical and dielectric characteristics of Ta2O5 thin films with specific examples from recent literature and the associated conduction mechanisms are summarized and discussed. Some suggestions to improve the electrical properties of the films are finally included. ©1998Kluwer Academic Publishers

S.s. Kamble - One of the best experts on this subject based on the ideXlab platform.

  • Quaternary Co1−x−yZnxCdyS thin films: A facile synthesis approach and its aptness for the applications in micro-devices
    Materials Letters, 2016
    Co-Authors: S.s. Kamble, Andrzej Sikora, S. L. Deshmukh, G.t. Chavan, V.s. Karande, S.t. Pawar, N.l. Tarwal, L.p. Deshmukh
    Abstract:

    Abstract The synthesis of multicomponent semiconducting thin films has become the subject of intensive research. The development of deposition-characterization techniques and property correlation and understanding of these materials are critical for the successful implementation of a whole new generation of advanced micro-devices. A wide range of discussion made in this article include facile chemical synthesis of Zn, Cd(CoS) thin films and characterization pertaining to the studies on compositional, morphological, optical and electrical transport aspects. The overall discussion involved herein will be useful to establish further engrossment of the researchers in the mentioned quaternary system.