The Experts below are selected from a list of 190572 Experts worldwide ranked by ideXlab platform
J B Kuo - One of the best experts on this subject based on the ideXlab platform.
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low voltage soi CMOS vlsi devices and circuits
2001Co-Authors: J B Kuo, Shihchia LinAbstract:Preface. Acknowlegments. Introduction. SOI CMOS Devices--Part I. SOI CMOS Devices--Part II. Fundamentals of SOI CMOS Circuits. SOI CMOS Digital Circuits. SOI CMOS Analog Circuits. PD SOI-Technology SPICE Models. Index.
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a 1 5 v full swing bootstrapped CMOS large capacitive load driver circuit suitable for low voltage CMOS vlsi
IEEE Journal of Solid-state Circuits, 1997Co-Authors: J H Lou, J B KuoAbstract:This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous.
Lianmao Peng - One of the best experts on this subject based on the ideXlab platform.
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graphene si CMOS hybrid hall integrated circuits
Scientific Reports, 2015Co-Authors: Le Huang, Zhiyong Zhang, Chengying Chen, Jianhua Jiang, Bingyan Chen, Hua Zhong, Lianmao PengAbstract:Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.
Teresa Galan - One of the best experts on this subject based on the ideXlab platform.
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broadband image sensor array based on graphene CMOS integration
Nature Photonics, 2017Co-Authors: Stijn Goossens, Gabriele Navickaite, Carles Monasterio, Shuchi Gupta, Juan Jose Piqueras, Raul Perez, Gregory Burwell, Ivan Nikitskiy, Tania Lasanta, Teresa GalanAbstract:Integrated circuits based on complementary metal-oxide–semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300–2,000 nm). The demonstrated graphene–CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies. Graphene–quantum dots on CMOS sensor offers broadband imaging.
Kazuo Nakazato - One of the best experts on this subject based on the ideXlab platform.
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2d optical imaging using photosystem i photosensor platform with 32x32 CMOS biosensor array
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Kiichi Niitsu, Taichi Sakabe, Mariko Miyachi, Yoshinori Yamanoi, Hiroshi Nishihara, Tatsuya Tomo, Kazuo NakazatoAbstract:This paper presents 2D imaging using photosensor platform with a newly-proposed large-scale CMOS biosensor array in 0.6-μm standard CMOS. The platform combines photosystem I (PSI) isolated from Thermosynechococcus elongatus and a large-scale CMOS biosensor array. PSI converts the absorbed photons into electrons, which are then sensed by the CMOS biosensor array. The prototyped photosensor enables CMOS-based 2D imaging using PSI for the first time.
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demonstration of 2d optical imaging using photosystem i photosensor platform with 3232 CMOS biosensor array
International New Circuits and Systems Conference, 2018Co-Authors: Kiichi Niitsu, Taichi Sakabe, Mariko Miyachi, Yoshinori Yamanoi, Hiroshi Nishihara, Tatsuya Tomo, Kazuo NakazatoAbstract:This paper presents 2D imaging using photo sensor platform with a newly-proposed large-scale CMOS bio sensor array in 0.6- μ standard CMOS. The platform combines photo system I (PSI) isolated from Thermosynechococcus elongatus and a large-scale CMOS bio sensor array. PSI converts the absorbed photons into electrons, which are then sensed by the CMOS bio sensor array. The prototyped photo sensor enables CMOS-based 2D imaging using PSI for the first time.
Wooyoung Choi - One of the best experts on this subject based on the ideXlab platform.
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performance optimization and improvement of silicon avalanche photodetectors in standard CMOS technology
IEEE Journal of Selected Topics in Quantum Electronics, 2018Co-Authors: Myungjae Lee, Wooyoung ChoiAbstract:This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs’ structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.
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effects of guard ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology
IEEE Electron Device Letters, 2012Co-Authors: Myungjae Lee, H Rucker, Wooyoung ChoiAbstract:We investigate the effects of guard-ring (GR) structures on the performance of silicon avalanche photodetectors (APDs) fabricated with the standard complementary metal-oxide-semiconductor (CMOS) technology. Four types of CMOS-compatible APDs (CMOS-APDs) based on the p+/ n-well junction with different GR structures are fabricated, and their electric-field profiles are simulated and analyzed. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth for CMOS-APDs are measured and compared. It is demonstrated that the GR realized with shallow trench isolation provides the best CMOS-APD performance.
