The Experts below are selected from a list of 29607 Experts worldwide ranked by ideXlab platform
I. Osamu - One of the best experts on this subject based on the ideXlab platform.
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Analog Circuit sizing with dynamic search window
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: F. Tomohiro, I. OsamuAbstract:In this paper an optimization method for Analog Circuit sizing is proposed. The proposed method is an estimation based method, and our goal is to achieve Analog Circuit sizing with practical computational cost. In order to apply the stochastic process model, which is used to estimate the objective function, to practical problems of Analog Circuit sizing, we propose the method with a dynamic search window. The experimental result shows that the Analog sizing of OPAMP was performed with 253 SPICE simulations and its CPU time was 9,430 seconds. This result illustrates the efficiency of our method
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ISCAS - Analog Circuit sizing with dynamic search window
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: F. Tomohiro, I. OsamuAbstract:In this paper an optimization method for Analog Circuit sizing is proposed. The proposed method is an estimation based method, and our goal is to achieve Analog Circuit sizing with practical computational cost. In order to apply the stochastic process model, which is used to estimate the objective function, to practical problems of Analog Circuit sizing, we propose the method with a dynamic search window. The experimental result shows that the Analog sizing of OPAMP was performed with 253 SPICE simulations and its CPU time was 9,430 seconds. This result illustrates the efficiency of our method.
Lihong Zhang - One of the best experts on this subject based on the ideXlab platform.
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Graph-Grammar-Based Analog Circuit Topology Synthesis
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Zhenxin Zhao, Lihong ZhangAbstract:Automatically constructing Analog Circuit topology according to specifications is always a challenging task, due to the high complexity and substantial design expertise required. This paper proposes a graph-grammar-based method that can efficiently and automatically generate Analog Circuit topologies, which can be applied to general Analog Circuit synthesis frameworks for Analog Circuit design. The topology generation process is encoded by constructing a binary tree, in which the leaf nodes are decomposed according to a set of grammar rules. In order to guarantee only unique Circuit structures to be generated, double isomorphism checks are applied at both tree structure level and Circuit transistor level. Our experimental results demonstrate the high efficiency and wide applicability of the proposed method.
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ISCAS - Graph-Grammar-Based Analog Circuit Topology Synthesis
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Zhenxin Zhao, Lihong ZhangAbstract:Automatically constructing Analog Circuit topology according to specifications is always a challenging task, due to the high complexity and substantial design expertise required. This paper proposes a graph-grammar-based method that can efficiently and automatically generate Analog Circuit topologies, which can be applied to general Analog Circuit synthesis frameworks for Analog Circuit design. The topology generation process is encoded by constructing a binary tree, in which the leaf nodes are decomposed according to a set of grammar rules. In order to guarantee only unique Circuit structures to be generated, double isomorphism checks are applied at both tree structure level and Circuit transistor level. Our experimental results demonstrate the high efficiency and wide applicability of the proposed method.
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Fast Performance Evaluation for Analog Circuit Synthesis Frameworks
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Zhenxin Zhao, Tuotian Liao, Lihong ZhangAbstract:Evaluating the performance of schematic-level un-sized Circuits is always a challenging task within the automated Analog Circuit synthesis process. One has to trade accuracy for efficiency in order to maintain efficient synthesis. This paper presents a new method of fast performance evaluation, which can be applied to general Analog Circuit synthesis frameworks. We propose to integrate graph-based symbolic analysis with the curve-fitting technique by using the gm/lD methodology. Both linear programming and nonlinear programming are utilized to validate the feasibility of un-sized Circuit topology with reference to the defined specifications. Our experimental results indicate high efficacy of the proposed method. It can significantly reduce the entire Circuit synthesis time by leaving a small number of Circuit topologies for detailed sizing and further evaluation.
F. Tomohiro - One of the best experts on this subject based on the ideXlab platform.
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Analog Circuit sizing with dynamic search window
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: F. Tomohiro, I. OsamuAbstract:In this paper an optimization method for Analog Circuit sizing is proposed. The proposed method is an estimation based method, and our goal is to achieve Analog Circuit sizing with practical computational cost. In order to apply the stochastic process model, which is used to estimate the objective function, to practical problems of Analog Circuit sizing, we propose the method with a dynamic search window. The experimental result shows that the Analog sizing of OPAMP was performed with 253 SPICE simulations and its CPU time was 9,430 seconds. This result illustrates the efficiency of our method
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ISCAS - Analog Circuit sizing with dynamic search window
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: F. Tomohiro, I. OsamuAbstract:In this paper an optimization method for Analog Circuit sizing is proposed. The proposed method is an estimation based method, and our goal is to achieve Analog Circuit sizing with practical computational cost. In order to apply the stochastic process model, which is used to estimate the objective function, to practical problems of Analog Circuit sizing, we propose the method with a dynamic search window. The experimental result shows that the Analog sizing of OPAMP was performed with 253 SPICE simulations and its CPU time was 9,430 seconds. This result illustrates the efficiency of our method.
Zhenxin Zhao - One of the best experts on this subject based on the ideXlab platform.
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Graph-Grammar-Based Analog Circuit Topology Synthesis
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Zhenxin Zhao, Lihong ZhangAbstract:Automatically constructing Analog Circuit topology according to specifications is always a challenging task, due to the high complexity and substantial design expertise required. This paper proposes a graph-grammar-based method that can efficiently and automatically generate Analog Circuit topologies, which can be applied to general Analog Circuit synthesis frameworks for Analog Circuit design. The topology generation process is encoded by constructing a binary tree, in which the leaf nodes are decomposed according to a set of grammar rules. In order to guarantee only unique Circuit structures to be generated, double isomorphism checks are applied at both tree structure level and Circuit transistor level. Our experimental results demonstrate the high efficiency and wide applicability of the proposed method.
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ISCAS - Graph-Grammar-Based Analog Circuit Topology Synthesis
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Zhenxin Zhao, Lihong ZhangAbstract:Automatically constructing Analog Circuit topology according to specifications is always a challenging task, due to the high complexity and substantial design expertise required. This paper proposes a graph-grammar-based method that can efficiently and automatically generate Analog Circuit topologies, which can be applied to general Analog Circuit synthesis frameworks for Analog Circuit design. The topology generation process is encoded by constructing a binary tree, in which the leaf nodes are decomposed according to a set of grammar rules. In order to guarantee only unique Circuit structures to be generated, double isomorphism checks are applied at both tree structure level and Circuit transistor level. Our experimental results demonstrate the high efficiency and wide applicability of the proposed method.
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Fast Performance Evaluation for Analog Circuit Synthesis Frameworks
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Zhenxin Zhao, Tuotian Liao, Lihong ZhangAbstract:Evaluating the performance of schematic-level un-sized Circuits is always a challenging task within the automated Analog Circuit synthesis process. One has to trade accuracy for efficiency in order to maintain efficient synthesis. This paper presents a new method of fast performance evaluation, which can be applied to general Analog Circuit synthesis frameworks. We propose to integrate graph-based symbolic analysis with the curve-fitting technique by using the gm/lD methodology. Both linear programming and nonlinear programming are utilized to validate the feasibility of un-sized Circuit topology with reference to the defined specifications. Our experimental results indicate high efficacy of the proposed method. It can significantly reduce the entire Circuit synthesis time by leaving a small number of Circuit topologies for detailed sizing and further evaluation.
Sudhanshu Shekhar Jamuar - One of the best experts on this subject based on the ideXlab platform.
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Low voltage Analog Circuit design techniques
IEEE Circuits and Systems Magazine, 2002Co-Authors: S. S. Rajput, Sudhanshu Shekhar JamuarAbstract:Analog signal processing is fast and can address real world problems. The applications of battery powered Analog and mixed mode electronic devices require designing Analog Circuits to operate at low voltage levels. In this paper, some of the issues facing Analog designers in implementing low voltage Circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for Analog Circuit structures along with their merits and demerits
