The Experts below are selected from a list of 117 Experts worldwide ranked by ideXlab platform

Dmitry Ponomarev - One of the best experts on this subject based on the ideXlab platform.

  • Register versioning a low complexity implementation of Register renaming in out of order microarchitectures
    International Conference on Parallel Processing, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Dmitry Ponomarev
    Abstract:

    Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an Architectural Register. Register versioning replaces the physical Register file with a simpler structure that integrates the physical Register file with an Architectural Register file, both having the same number of entries, namely the number of Architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.

  • energy efficient renaming with Register versioning
    International Symposium on Low Power Electronics and Design, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Ju-young Jung, Dmitry Ponomarev
    Abstract:

    We propose an energy-efficient implementation of Register renaming mechanism for high-performance superscalar microprocessors. We use version numbers to identify various instances of each Architectural Register. This enables the use of an unified Register file to hold the current instances of an Architectural Register and its committed value in a shadow bitcells and to simplify Register renaming and Register management. Across the SPEC 2000 benchmarks, the proposed mechanism comes within 6% of the performance of a traditional out-of-order design. An average savings of 20% on the energy spent in renaming, Register management and instruction commitment is realized compared to a traditional design.

  • ICPP - Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures
    2009 International Conference on Parallel Processing, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Dmitry Ponomarev
    Abstract:

    Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an Architectural Register. Register versioning replaces the physical Register file with a simpler structure that integrates the physical Register file with an Architectural Register file, both having the same number of entries, namely the number of Architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.

  • ISLPED - Energy-efficient renaming with Register versioning
    Proceedings of the 14th ACM IEEE international symposium on Low power electronics and design - ISLPED '09, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Ju-young Jung, Dmitry Ponomarev
    Abstract:

    We propose an energy-efficient implementation of Register renaming mechanism for high-performance superscalar microprocessors. We use version numbers to identify various instances of each Architectural Register. This enables the use of an unified Register file to hold the current instances of an Architectural Register and its committed value in a shadow bitcells and to simplify Register renaming and Register management. Across the SPEC 2000 benchmarks, the proposed mechanism comes within 6% of the performance of a traditional out-of-order design. An average savings of 20% on the energy spent in renaming, Register management and instruction commitment is realized compared to a traditional design.

  • Early Register Deallocation Mechanisms Using Checkpointed Register Files
    IEEE Transactions on Computers, 2006
    Co-Authors: Oğuz Ergin, Dmitry Ponomarev, Deniz Balkan, Kanad Ghose
    Abstract:

    Modern superscalar microprocessors need sizable Register files to support a large number of in-flight instructions for exploiting instruction level parallelism (ILP). An alternative to building large Register files is to use a smaller number of Registers, but manage them more effectively. More efficient management of Registers can also result in higher performance if the reduction of the Register file size is not the goal. Traditional Register file management mechanisms deallocate a physical Register only when the next instruction writing to the same destination Architectural Register commits. In this paper, we propose several techniques for deallocating physical Registers much earlier. Our designs rely on the use of a checkpointed Register file (CRF), where a local shadow copy of each bitcell is used to temporarily save the values of the early deallocated Registers should they be needed to recover from branch mispredictions or to reconstruct the precise state after exceptions or interrupts. The proposed techniques try to release Registers as soon as possible and are more aggressive than the previously proposed schemes for early deallocation of Registers

Kanad Ghose - One of the best experts on this subject based on the ideXlab platform.

  • Register versioning a low complexity implementation of Register renaming in out of order microarchitectures
    International Conference on Parallel Processing, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Dmitry Ponomarev
    Abstract:

    Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an Architectural Register. Register versioning replaces the physical Register file with a simpler structure that integrates the physical Register file with an Architectural Register file, both having the same number of entries, namely the number of Architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.

  • energy efficient renaming with Register versioning
    International Symposium on Low Power Electronics and Design, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Ju-young Jung, Dmitry Ponomarev
    Abstract:

    We propose an energy-efficient implementation of Register renaming mechanism for high-performance superscalar microprocessors. We use version numbers to identify various instances of each Architectural Register. This enables the use of an unified Register file to hold the current instances of an Architectural Register and its committed value in a shadow bitcells and to simplify Register renaming and Register management. Across the SPEC 2000 benchmarks, the proposed mechanism comes within 6% of the performance of a traditional out-of-order design. An average savings of 20% on the energy spent in renaming, Register management and instruction commitment is realized compared to a traditional design.

  • Managing datapath resources in an out-of-order processor for performance and energy efficiency
    2009
    Co-Authors: Kanad Ghose, Hui Zeng
    Abstract:

    High-end superscalar processors are using faster clocks, smaller feature sizes, and larger instruction windows, and their performance is increasingly being affected by wire delays. Design changes at the microArchitectural level can improve efficiency and performance, while incorporating advances in manufacturing technologies. This work presents a number of such techniques to improve performance and energy efficiency in out-of-order processors. With increasing wire delays and the use of faster clocks, Register file access delays can limit performance. To address this problem, we present a Register file cache (RFC) design that provides significant dynamic power savings in accessing Register operands with negligible performance loss, for a superscalar datapath with a Register file that requires multi-cycle access. The new design segregates the cache into two parts, namely a FIFO cache for short-term values consumed within a few cycles of production, and a small associative cache for values to be consumed over a longer period. The new design has lower complexity than a single fully associative cache design, and is very effective in caching long-term values. We also propose an energy-efficient implementation of a Register renaming mechanism, using version numbers to identify various instances of each Architectural Register. A unified Register file is used to hold the current instances of an Architectural Register, together with its committed value, in shadow bitcells that simplify Register renaming and Register management. The resulting design offers performance similar to traditional hardware, while being considerably simpler. To support large instruction windows, efficient instruction commitment mechanisms are critical. To reduce the energy needed to support large instruction windows, we propose a new hardware design for a checkpoint-based commitment mechanism. The design is based on simpler structures and bit masking operations without complicated counter hardware, and allows out-of-order release of checkpoints. These features support a larger instruction window compared to traditional designs and extract a higher degree of Instruction Level Parallelism (ILP), requiring approximately the same hardware investment but with greater energy efficiency. Finally, we introduce another alternative instruction commitment mechanism using a Reorder Buffer (ROB) that commits a group of consecutive instructions atomically to support a larger instruction window with the same resources. This mechanism conservatively sets up entries only for instructions providing the latest update to an Architectural Register from that group, so that other Registers can be released earlier compared to a traditional design. The augmented ROB-based datapath increases the effective size of the ROB and the effective number of physical Registers, offering a significant performance gain.

  • ICPP - Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures
    2009 International Conference on Parallel Processing, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Dmitry Ponomarev
    Abstract:

    Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an Architectural Register. Register versioning replaces the physical Register file with a simpler structure that integrates the physical Register file with an Architectural Register file, both having the same number of entries, namely the number of Architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.

  • ISLPED - Energy-efficient renaming with Register versioning
    Proceedings of the 14th ACM IEEE international symposium on Low power electronics and design - ISLPED '09, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Ju-young Jung, Dmitry Ponomarev
    Abstract:

    We propose an energy-efficient implementation of Register renaming mechanism for high-performance superscalar microprocessors. We use version numbers to identify various instances of each Architectural Register. This enables the use of an unified Register file to hold the current instances of an Architectural Register and its committed value in a shadow bitcells and to simplify Register renaming and Register management. Across the SPEC 2000 benchmarks, the proposed mechanism comes within 6% of the performance of a traditional out-of-order design. An average savings of 20% on the energy spent in renaming, Register management and instruction commitment is realized compared to a traditional design.

Oğuz Ergin - One of the best experts on this subject based on the ideXlab platform.

  • Complexity-Effective Rename Table Design for Rapid Speculation Recovery
    2012
    Co-Authors: Görkem Aşılıoğlu, Emine Merve Kaya, Oğuz Ergin, Söğütözü Cad, No Söğütözü
    Abstract:

    Abstract. Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The Register rename logic includes a mapping table that holds the physical Register identifiers assigned to each Architectural Register. This mapping table needs to be recovered to its correct state when a branch prediction occurs. In this paper we propose a scalable rename table design that allows fast recovery on branch predictions. A FIFO scheme is applied with a distributed rename table structure that holds a variable number of checkpoints specific to each Architectural Register. Our results show that although the area of the rename table is increased, it is possible to recover from a branch misprediction in at worst 2 cycles

  • Exploiting Inactive Rename Slots for Detecting Soft Errors
    2012
    Co-Authors: Mehmet Kayaalp, Oğuz Ergin, Osman S. Ünsal, Mateo Valero
    Abstract:

    Abstract. Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical Register mapping for each Architectural Register and a logic for checking intra-group dependencies. This logic checking consists of a number of comparators that compares the values of destination and source Registers. Previous research has shown that the full capacity of the dependency checking logic is not used at each cycle. In this paper we propose some techniques that make use of the unused capacity of the dependency checking logic of the rename stage in order to detect soft errors that occur on the Register tags while the instructions are passing through the frontend of the processor

  • Exploiting the Dependency Checking Logic of the Rename Stage for Soft Error Detection
    2010
    Co-Authors: Oğuz Ergin, Osman S. Ünsal, Gülay Yalçın, Mateo Valero
    Abstract:

    Abstract. Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical Register mapping for each Architectural Register and a logic for checking intra-group dependencies which consists of a number of comparators that compares the values of destination and source Registers. Previous research has shown that the full capacity of the dependency checking logic is not used at each cycle. In this paper we propose a technique that makes use of the unused capacity of the dependency checking logic of the rename stage in order to detect soft errors that occur on the Register tags while the instructions are passing through the frontend of the processor.

  • ARCS - Complexity-Effective rename table design for rapid speculation recovery
    Architecture of Computing Systems - ARCS 2010, 2010
    Co-Authors: Görkem Aşılıoğlu, Emine Merve Kaya, Oğuz Ergin
    Abstract:

    Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The Register rename logic includes a mapping table that holds the physical Register identifiers assigned to each Architectural Register. This mapping table needs to be recovered to its correct state when a branch prediction occurs. In this paper we propose a scalable rename table design that allows fast recovery on branch predictions. A FIFO scheme is applied with a distributed rename table structure that holds a variable number of checkpoints specific to each Architectural Register. Our results show that although the area of the rename table is increased, it is possible to recover from a branch misprediction in at worst 2 cycles.

  • ARCS - Exploiting inactive rename slots for detecting soft errors
    Architecture of Computing Systems - ARCS 2010, 2010
    Co-Authors: Mehmet Kayaalp, Oğuz Ergin, Osman Unsal, Mateo Valero
    Abstract:

    Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical Register mapping for each Architectural Register and a logic for checking intra-group dependencies. This logic checking consists of a number of comparators that compares the values of destination and source Registers. Previous research has shown that the full capacity of the dependency checking logic is not used at each cycle. In this paper we propose some techniques that make use of the unused capacity of the dependency checking logic of the rename stage in order to detect soft errors that occur on the Register tags while the instructions are passing through the frontend of the processor.

Hui Zeng - One of the best experts on this subject based on the ideXlab platform.

  • Register versioning a low complexity implementation of Register renaming in out of order microarchitectures
    International Conference on Parallel Processing, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Dmitry Ponomarev
    Abstract:

    Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an Architectural Register. Register versioning replaces the physical Register file with a simpler structure that integrates the physical Register file with an Architectural Register file, both having the same number of entries, namely the number of Architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.

  • energy efficient renaming with Register versioning
    International Symposium on Low Power Electronics and Design, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Ju-young Jung, Dmitry Ponomarev
    Abstract:

    We propose an energy-efficient implementation of Register renaming mechanism for high-performance superscalar microprocessors. We use version numbers to identify various instances of each Architectural Register. This enables the use of an unified Register file to hold the current instances of an Architectural Register and its committed value in a shadow bitcells and to simplify Register renaming and Register management. Across the SPEC 2000 benchmarks, the proposed mechanism comes within 6% of the performance of a traditional out-of-order design. An average savings of 20% on the energy spent in renaming, Register management and instruction commitment is realized compared to a traditional design.

  • Managing datapath resources in an out-of-order processor for performance and energy efficiency
    2009
    Co-Authors: Kanad Ghose, Hui Zeng
    Abstract:

    High-end superscalar processors are using faster clocks, smaller feature sizes, and larger instruction windows, and their performance is increasingly being affected by wire delays. Design changes at the microArchitectural level can improve efficiency and performance, while incorporating advances in manufacturing technologies. This work presents a number of such techniques to improve performance and energy efficiency in out-of-order processors. With increasing wire delays and the use of faster clocks, Register file access delays can limit performance. To address this problem, we present a Register file cache (RFC) design that provides significant dynamic power savings in accessing Register operands with negligible performance loss, for a superscalar datapath with a Register file that requires multi-cycle access. The new design segregates the cache into two parts, namely a FIFO cache for short-term values consumed within a few cycles of production, and a small associative cache for values to be consumed over a longer period. The new design has lower complexity than a single fully associative cache design, and is very effective in caching long-term values. We also propose an energy-efficient implementation of a Register renaming mechanism, using version numbers to identify various instances of each Architectural Register. A unified Register file is used to hold the current instances of an Architectural Register, together with its committed value, in shadow bitcells that simplify Register renaming and Register management. The resulting design offers performance similar to traditional hardware, while being considerably simpler. To support large instruction windows, efficient instruction commitment mechanisms are critical. To reduce the energy needed to support large instruction windows, we propose a new hardware design for a checkpoint-based commitment mechanism. The design is based on simpler structures and bit masking operations without complicated counter hardware, and allows out-of-order release of checkpoints. These features support a larger instruction window compared to traditional designs and extract a higher degree of Instruction Level Parallelism (ILP), requiring approximately the same hardware investment but with greater energy efficiency. Finally, we introduce another alternative instruction commitment mechanism using a Reorder Buffer (ROB) that commits a group of consecutive instructions atomically to support a larger instruction window with the same resources. This mechanism conservatively sets up entries only for instructions providing the latest update to an Architectural Register from that group, so that other Registers can be released earlier compared to a traditional design. The augmented ROB-based datapath increases the effective size of the ROB and the effective number of physical Registers, offering a significant performance gain.

  • ICPP - Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures
    2009 International Conference on Parallel Processing, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Dmitry Ponomarev
    Abstract:

    Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an Architectural Register. Register versioning replaces the physical Register file with a simpler structure that integrates the physical Register file with an Architectural Register file, both having the same number of entries, namely the number of Architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.

  • ISLPED - Energy-efficient renaming with Register versioning
    Proceedings of the 14th ACM IEEE international symposium on Low power electronics and design - ISLPED '09, 2009
    Co-Authors: Hui Zeng, Kanad Ghose, Ju-young Jung, Dmitry Ponomarev
    Abstract:

    We propose an energy-efficient implementation of Register renaming mechanism for high-performance superscalar microprocessors. We use version numbers to identify various instances of each Architectural Register. This enables the use of an unified Register file to hold the current instances of an Architectural Register and its committed value in a shadow bitcells and to simplify Register renaming and Register management. Across the SPEC 2000 benchmarks, the proposed mechanism comes within 6% of the performance of a traditional out-of-order design. An average savings of 20% on the energy spent in renaming, Register management and instruction commitment is realized compared to a traditional design.

Christof Fetzer - One of the best experts on this subject based on the ideXlab platform.

  • Between All and Nothing–Versatile Aborts in Hardware Transactional Memory
    2015
    Co-Authors: Stephan Diestelhorst, Martin Nowack, Michael Spear, Christof Fetzer
    Abstract:

    Hardware Transactional Memory (HTM) implementations are becoming available in commercial, off-the-shelf components. While generally comparable, some implementations deviate from the strict all-or-nothing property of pure Transactional Memory. We analyse these deviations and find that with small modifications, they can be used to accelerate and simplify both transactional and non-transactional programming constructs. At the heart of our extensions we enable access to the transaction's full Register state in the abort handler in an existing HTM without extending the Architectural Register state. Access to the full Register state enables applications in both transactional and non-transactional parallel programming: hybrid transactional memory; transactional escape actions; transactional suspend/resume; and alert-on-update.

  • SPAA - Brief announcement: between all and nothing - versatile aborts in hardware transactional memory
    Proceedings of the 25th ACM symposium on Parallelism in algorithms and architectures - SPAA '13, 2013
    Co-Authors: Stephan Diestelhorst, Martin Nowack, Michael Spear, Christof Fetzer
    Abstract:

    Hardware Transactional Memory (HTM) implementations are becoming available in commercial, off-the-shelf components. While generally comparable, some implementations deviate from the strict all-or-nothing property of pure Transactional Memory. We analyse these deviations and find that with small modifications, they can be used to accelerate and simplify both transactional and non-transactional programming constructs. At the heart of our extensions we enable access to the transaction's full Register state in the abort handler in an existing HTM without extending the Architectural Register state. Access to the full Register state enables applications in both transactional and non-transactional parallel programming: hybrid transactional memory; transactional escape actions; transactional suspend/resume; and alert-on-update.

  • SPAA - Between all and nothing - versatile aborts in hardware transactional memory
    Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures, 2013
    Co-Authors: Stephan Diestelhorst, Martin Nowack, Michael Spear, Christof Fetzer
    Abstract:

    Hardware Transactional Memory (HTM) implementations are becoming available in commercial, off-the-shelf components. While generally comparable, some implementations deviate from the strict all-or-nothing property of pure Transactional Memory. We analyse these deviations and find that with small modifications, they can be used to accelerate and simplify both transactional and non-transactional programming constructs. At the heart of our extensions we enable access to the transaction's full Register state in the abort handler in an existing HTM without extending the Architectural Register state. Access to the full Register state enables applications in both transactional and non-transactional parallel programming: hybrid transactional memory; transactional escape actions; transactional suspend/resume; and alert-on-update.