The Experts below are selected from a list of 25203 Experts worldwide ranked by ideXlab platform
Sunil P. Khatri - One of the best experts on this subject based on the ideXlab platform.
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circuit level design of a hardware hash unit for use in modern Microprocessors
Great Lakes Symposium on VLSI, 2017Co-Authors: Abbas Fairouz, Monther Abusultan, Sunil P. KhatriAbstract:Modern Microprocessors contain several Special Function Units (SFUs) such as specialized arithmetic units, cryptographic processors, etc. In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used, and place new demands on the microprocessor. Hashing is a key algorithm that is extensively used in such applications. Hashing is typically performed in software. Thus, implementing a hardware-based hash unit on a modern microprocessor would potentially increase performance significantly. In this paper, we present the circuit design for a hardware hash unit (HU) for modern Microprocessors, using a 45nm technology. Our proposed hardware hash unit is based on the use of a CAM to implement each bin of the hash function. We simulate the HU circuit and compare it with a traditional CAM design. We demonstrate an average power reduction of 5.48x using the HU over the traditional CAM. Also, we show that the HU can operate at a maximum frequency of 1.39 GHz (after accounting for process, voltage and temperature (PVT) variations and accounting for wiring parasitics). Furthermore, we present the delay, power and area trade-offs of the HU design with varying hash table sizes.
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a novel hardware hash unit design for modern Microprocessors
International Conference on Computer Design, 2016Co-Authors: Abbas Fairouz, Monther Abusultan, Sunil P. KhatriAbstract:Historically, microprocessor instructions were designed in order to obtain high performance on integer and floating point computations. Today's applications, however, demand high performance for cloud computing, web-based search engines, network applications, and social media tasks. Such software applications involve an extensive use of hashing in their computation. Hashing can reduce the complexity of search and lookup from O(n) to O(n/k), where k bins are used. In modern Microprocessors hashing is done in software. In this paper, we propose a novel hardware hash unit design for use in modern Microprocessors. We present the design of the Hash Unit (HU) at the micro-architecture level. We simulate the new HU to compare its performance with a software-based hash implementation. We demonstrate a significant speed-up (up to 12×) for the HU. Furthermore, the performance scales elegantly with increasing database size and application diversity, without increasing the hardware cost.
E.l. Schwartz - One of the best experts on this subject based on the ideXlab platform.
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Micro-hardware implementation of a pattern recognition algorithm on a neuron-based multiprocessor system in a real-time environment
[Proceedings] 1991 IEEE International Joint Conference on Neural Networks, 1991Co-Authors: E.l. SchwartzAbstract:The authors present an experimental study on a system which implements a pattern recognition algorithm (W.C. Lin, K.S. Fu, 1965, 1966) with a set of artificial neuron elements emulated on a multi-microprocessor hardware system. The algorithm is believed to be good for parallel processing utilizing the concept of information content, or entropy. The system used for the implementation study consists of four commercially available iSBC 286/12 single board microcomputers. They are configured to operate in parallel within the environment of the real-time operating system iRMX286. Thus, it is a multi-microprocessor and multitasking real-time processing hardware system. It is shown that the system with four Microprocessors is 3.8 times faster than a single processor in operation speed with a recognition rate of 95%. Since the algorithm is a regionalism process in the feature space, the number of regions, and thus the number of Microprocessors operating in parallel, can be increased to satisfy specific real-time requirements.
Neeti Khullar - One of the best experts on this subject based on the ideXlab platform.
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generation of software tools from processor descriptions for hardware software codesign
Design Automation Conference, 1997Co-Authors: Mark R Hartoog, James A Rowson, Prakash Reddy, Soumya Desai, Douglas D Dunlop, Edwin A Harcourt, Neeti KhullarAbstract:An experimental set of tools that generate instruction set simulators,assemblers, and disassemblers from a single description wasdeveloped to test if retargetable development tools would work forcommercial DSP processors and Microprocessors. The processorinstruction set was described using a language called nML. TheTMS320C50 DSP processor and the ARM7 microprocessor weremodeled in nML. The resulting instruction set models executeabout 25,000 instructions per second, and compiled instruction setsimulation models execute about 150,000 instructions per second.The viability of this approach and the deficiencies of nML are discussed.
Rajendran Nair - One of the best experts on this subject based on the ideXlab platform.
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effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance Microprocessors
IEEE Journal of Solid-state Circuits, 2003Co-Authors: James W Tschanz, Siva G Narendra, Rajendran NairAbstract:Adaptive supply voltage as well as adaptive body bias may be used to control the frequency and leakage distribution of fabricated microprocessor dies. Test chip measurements show that adaptive V/sub CC/ is effective in reducing the impact of parameter variations on frequency, active power, and leakage power of Microprocessors when 20 mV V/sub CC/ resolution is used. Using adaptive V/sub CC/ together with adaptive V/sub BS/ or within-die body bias is much more effective than using any of them individually.
Ravi Mahajan - One of the best experts on this subject based on the ideXlab platform.
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IPACK2005-73486 ASME INTERPACK 2005 IPACK2005-73486 THERMAL BASED OPTIMIZATION OF FUNCTIONAL BLOCK DISTRIBUTIONS IN A NON- UNIFORMLY POWERED DIE
2020Co-Authors: Abhijit Kaisare, Dereje Agonafer, A Haji-shiekh, Greg Chrysler, Ravi MahajanAbstract:ABSTRACT Microprocessors continue to grow in capabilities, complexity and performance. The current generation of Microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of Microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 x 4 and 6x6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.
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DEVELOPMET OF AN ANALYTICAL MODEL TO A TEMPERATURE DISTRIBUTION OF FIRST LEVEL PACKAGE WITH A NON-UNIFORMLY POWERED DIE
2020Co-Authors: Abhijit Kaisare, Dereje Agonafer, Greg Chrysler, A Haji-sheikh, Ravi MahajanAbstract:ABSTRACT Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of Microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model
