The Experts below are selected from a list of 114 Experts worldwide ranked by ideXlab platform

Chihoon Shin - One of the best experts on this subject based on the ideXlab platform.

Seongwoon Kim - One of the best experts on this subject based on the ideXlab platform.

Scott C.3 Smith - One of the best experts on this subject based on the ideXlab platform.

  • Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology.
    Journal of Low Power Electronics & Applications, 2015
    Co-Authors: Liang Zhou, Ravi2 Parameswaran, Farhad A.2 Parsan, Scott C.3 Smith, Jia Di4
    Abstract:

    This paper develops an ultra-low power Asynchronous Circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous Circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL Circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster. [ABSTRACT FROM AUTHOR]

  • bit wise mtncl an ultra low power bit wise pipelined Asynchronous Circuit design methodology
    International Midwest Symposium on Circuits and Systems, 2010
    Co-Authors: Liang Zhou, Scott C.3 Smith
    Abstract:

    This paper develops an ultra-low power design methodology for bit-wise pipelined Asynchronous Circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL Circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation with a reasonable speed penalty compared to the all low-Vt design, requires less energy/operation, and has no area overhead.

Alex Yakovlev - One of the best experts on this subject based on the ideXlab platform.

  • high level Asynchronous concepts at the interface between analog and digital worlds
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
    Co-Authors: Jonathan Beaumont, Andrey Mokhov, Danil Sokolov, Alex Yakovlev
    Abstract:

    Asynchronous Circuits are becoming increasingly important in system design for Internet of Things, where they orchestrate the interface between big synchronous computation components and the analog environment, which is inherently Asynchronous and has high uncertainty with respect to power supply, temperature, and long-term aging effects. However, wide adoption of Asynchronous Circuits by industrial users is hindered by a steep learning curve for Asynchronous control models, such as signal transition graphs (STGs), that are developed by the academic community for specification, verification, and synthesis of Asynchronous Circuits. In this paper, we introduce a novel high-level description language for Asynchronous Circuits, which is based on behavioral concepts —high-level descriptions of Asynchronous Circuit requirements, that can be shared, reused, and extended by users, and can be automatically translated to STGs for further processing by conventional Asynchronous and synchronous electronic design automation tools, such as Petrify and Mpsat. Our aim is to simplify the process of capturing system requirements in the form of a formal specification, and to promote behavioral concepts as a means for design reuse. The proposed design flow is fully automated in open-source toolsuite Workcraft, and is applied to the development of an Asynchronous power regulator.

  • checking signal transition graph implementability by symbolic bdd traversal
    European Design and Test Conference, 1995
    Co-Authors: Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Enric Pastor, O Roig, Alex Yakovlev
    Abstract:

    This paper defines conditions for a Signal Transition Graph to be implemented by an Asynchronous Circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification under the restricted input-output interface between the design and the environment, i.e., when no additional interface signals are allowed to be added to the design. We develop algorithms and present experimental results of using BDD-traversal for checking STG implementability. These results demonstrate efficiency of the symbolic approach and show a way of improving existing tools for STG-based Asynchronous Circuit design. >

Ralf Wollowski - One of the best experts on this subject based on the ideXlab platform.

  • decomposition in Asynchronous Circuit design
    Foundations of Software Technology and Theoretical Computer Science, 2002
    Co-Authors: Walter Vogler, Ralf Wollowski
    Abstract:

    Signal Transition Graphs (STGs) are a version of Petri nets for the specification of Asynchronous Circuit behaviour. It has been suggested to decompose such a specification as a first step; this leads to a modular implementation, which can support Circuit synthesis by possibly avoiding state explosion or allowing the use of library elements.We present a decomposition algorithm and formally prove it correct, where an interesting aspect is the use of a bisimulation with angelic nondeterminism. In contrast to similar approaches in the literature, our algorithm is very generally applicable. We show that transition contraction - the main operation in the algorithm - can be applied with fewer restrictions than known so far. We also prove that deletion of redundant places can be used in the algorithm, which turns out to be very useful in examples.