The Experts below are selected from a list of 654 Experts worldwide ranked by ideXlab platform
Liu Zhiju - One of the best experts on this subject based on the ideXlab platform.
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synchronous Reset and Asynchronous Reset in asic design
Shandong Electronics, 2005Co-Authors: Liu ZhijuAbstract:Reset is one of the key problems in ASIC design, it will directly influence the performance of the whole design if it is done properly or not. This paper discussed and analyzed the synchronous Reset and the Asynchronous Reset from several different perspectives. A Comparison between them in the advantages and the disadvantages was conducted. The metastability problem, exiting in the process of Asynchronous Reset, was resolved by adding the two-level Reset synchronizer logic and using Reset distribution buffer tree.
Luo Lan - One of the best experts on this subject based on the ideXlab platform.
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metastability and solution in Asynchronous Reset designs
Journal of Electron Devices, 2002Co-Authors: Luo LanAbstract:Although an Asynchronous Reset is a safe way to reliably Reset circuitry, removal of an Asynchronous Reset can cause metastability if not done properly. A proper way to design with Asynchronous Resets by adding the Reset synchronizer logic and using Reset distribute buffer tree to allow Asynchronous Reset of the design and to insure synchronous Reset removal to permit safe restoration of normal design functionality was given in this paper.
Xiaoni Wei - One of the best experts on this subject based on the ideXlab platform.
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Asynchronous Reset design architecture
IEEE International Conference on Solid-State and Integrated Circuit Technology, 2014Co-Authors: Xiaoni WeiAbstract:With the increased complexity of digital design, the Reset architecture used in current nanometer-scale designs has become complicated. Design and implementation of Reset architecture is therefore a crucial part of any design. This paper analyses the pros and cons of synchronous and Asynchronous Resets. We have presented our current understanding of Reset design issues in real chip design when choosing Reset strategy. Based on our rich industry experience, we are providing a practical, effective and reliable Reset strategy, which will be applicable in modern nanometer-scale digital chip design.
Domenic Forte - One of the best experts on this subject based on the ideXlab platform.
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a weak Asynchronous Reset ares puf using start up characteristics of null conventional logic gates
International Test Conference, 2020Co-Authors: Sreeja Chowdhury, Rabin Yu Acharya, William Boullion, Andrew Felder, Mark Howard, Domenic ForteAbstract:Physical unclonable functions (PUFs) are widely researched security primitive in the digital and analog domain but have yet to be explored for Asynchronous circuits. In this paper, we propose novel optimization methods to design a weak Asynchronous Reset (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates as a source of entropy. We employ two different methods to design the ARES PUF. The first includes traditional delay matching techniques using linear programming-based optimization, whereas the second one uses the genetic algorithm (GA) with delay matching as a fitness function. Both methodologies are explained with analysis and design specifications required to model NCL TH22 gates to achieve PUF characteristics. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison. Simulation results using initial delay matching techniques at 90nm and 65nm technology in HSPICE shows that the proposed ARES PUF has a uniqueness of 49.98% and reliability of 96.53% across $V_{DD} $ variation (± 10%) and 93.39% across temperature variation $(0^{\circ}C- 80^{\circ}C)$. Whereas, the GA method can optimize NCL cells to form a PUF with 49% uniqueness at 65nm with an average reliability of 96.4% across $V_{DD} $ and 93.82% across temperature. Preliminary silicon results for proposed TH22 at TSMC 90nm technology node shows a 34% improvement in uniqueness compared to standard TH22 gate with best-case uniqueness of 53.3% and reliability of 100% respectively across repeated measurements (noise). Unlike standard TH22, standard TH44 performs better with 47.62% best-case uniqueness and 98.1% reliability.1
Neeraj Pradhan - One of the best experts on this subject based on the ideXlab platform.
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at speed testing of Asynchronous Reset de assertion faults
International Conference on VLSI Design, 2012Co-Authors: Arvind Jain, Maheedhar Jalasutram, Srinivas Vooka, Prasun Nair, Neeraj PradhanAbstract:In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the Asynchronous Reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on Asynchronous Reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.