The Experts below are selected from a list of 291 Experts worldwide ranked by ideXlab platform
Volkan Kursun - One of the best experts on this subject based on the ideXlab platform.
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Voltage optimization for simultaneous energy efficiency and Temperature Variation resilience in CMOS circuits
Microelectronics Journal, 2020Co-Authors: R. Kumar, Volkan KursunAbstract:A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and Temperature Variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay Variations when the Temperature fluctuates are identified for a diverse set of circuits in 180 and 65 nm CMOS technologies. Circuits display Temperature Variation insensitive propagation delay when operated at a supply voltage 44-47% lower than the nominal supply voltage (V DD = 1.8 V) in a 180 nm CMOS technology. Similarly, the optimum supply voltages are 67-68% lower than the nominal supply voltage (V DD = 1.0 V) in a 65 nm CMOS technology. At scaled supply voltages, integrated circuits consume lower power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for Temperature Variation insensitive circuit performance is, therefore, particularly attractive for low-power applications with relaxed speed requirements. A new design methodology based on threshold voltage optimization for achieving Temperature Variation insensitive circuit speed is also evaluated. The energy per cycle and the propagation delay at the supply and threshold voltages providing Temperature Variation insensitive circuit performance, minimum energy-delay product, and minimum energy are compared. Results indicate that low-power operation and Temperature Variation tolerance can be simultaneously achieved with the proposed techniques. © 2007 Elsevier Ltd. All rights reserved
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Voltage optimization for simultaneous energy efficiency and Temperature Variation resilience in CMOS circuits
Microelectronics Journal, 2007Co-Authors: R. Kumar, Volkan KursunAbstract:A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and Temperature Variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay Variations when the Temperature fluctuates are identified for a diverse set of circuits in 180 and 65nm CMOS technologies. Circuits display Temperature Variation insensitive propagation delay when operated at a supply voltage 44-47% lower than the nominal supply voltage (V"D"D=1.8V) in a 180nm CMOS technology. Similarly, the optimum supply voltages are 67-68% lower than the nominal supply voltage (V"D"D=1.0V) in a 65nm CMOS technology. At scaled supply voltages, integrated circuits consume lower power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for Temperature Variation insensitive circuit performance is, therefore, particularly attractive for low-power applications with relaxed speed requirements. A new design methodology based on threshold voltage optimization for achieving Temperature Variation insensitive circuit speed is also evaluated. The energy per cycle and the propagation delay at the supply and threshold voltages providing Temperature Variation insensitive circuit performance, minimum energy-delay product, and minimum energy are compared. Results indicate that low-power operation and Temperature Variation tolerance can be simultaneously achieved with the proposed techniques.
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Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology
2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006Co-Authors: R. Kumar, Volkan KursunAbstract:A design methodology based on optimizing the supply voltage for simultaneously achieving energy efficiency and Temperature Variation insensitive circuit performance is presented in this paper. Circuits exhibit Temperature Variation insensitive delay characteristics when operated at a supply voltage 67% to 68% lower than the nominal supply voltage. At scaled supply voltages, integrated circuits consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for Temperature Variation insensitive circuit performance is, therefore, particularly attractive for low power applications with relaxed speed requirements. The supply voltages that yield minimum energy and minimum energy-delay product are identified at two different Temperatures for circuits in a 65 nm CMOS technology. The energy and speed at the supply voltages providing Temperature Variation insensitive propagation delay, minimum energy, and minimum energy-delay product are compared. Results indicate that energy efficient integrated circuits with deeply scaled supply voltages can also be made insensitive to Temperature fluctuations by considering the Temperature dependence of speed in the supply voltage optimization process.
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Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison
2006 IEEE International SOC Conference, 2006Co-Authors: R. Kumar, Volkan KursunAbstract:In this paper, the supply and threshold voltage optimization techniques to achieve Temperature Variation insensitive circuit performance are compared. The speed and energy tradeoffs with the two optimization techniques are presented.
Shi Yafeng - One of the best experts on this subject based on the ideXlab platform.
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general characteristics of Temperature Variation in china during the last two millennia
Geophysical Research Letters, 2002Co-Authors: Bao Yang, Achim Braeuning, Kathleen R Johnson, Shi YafengAbstract:Three alternate China-wide Temperature composites covering the last 2000 years were established by combining multiple paleoclimate proxy records obtained from ice cores, tree rings, lake sediments and historical documents. Five periods of Temperature Variation can be identified: a warm stage in AD 0–240, a cold interval between AD 240 and 800, a return to warm conditions from AD 800–1400, including the Medieval Warm Period between AD 800–1100, the cool Little Ice Age period between 1400–1920, and the present warm stage since 1920. Regional Temperature Variation is found during AD 800–1100, when warm conditions occurred in Eastern China and in the northeastern Tibetan Plateau and in AD 1150–1380, when the southern Tibetan Plateau experienced a warm interval. In contrast, evidence for cool conditions during the LIA is more consistent among the proxy records. The Temperature reconstructions for China and the Northern Hemisphere show good agreement over the past millennium.
R. Kumar - One of the best experts on this subject based on the ideXlab platform.
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Voltage optimization for simultaneous energy efficiency and Temperature Variation resilience in CMOS circuits
Microelectronics Journal, 2020Co-Authors: R. Kumar, Volkan KursunAbstract:A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and Temperature Variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay Variations when the Temperature fluctuates are identified for a diverse set of circuits in 180 and 65 nm CMOS technologies. Circuits display Temperature Variation insensitive propagation delay when operated at a supply voltage 44-47% lower than the nominal supply voltage (V DD = 1.8 V) in a 180 nm CMOS technology. Similarly, the optimum supply voltages are 67-68% lower than the nominal supply voltage (V DD = 1.0 V) in a 65 nm CMOS technology. At scaled supply voltages, integrated circuits consume lower power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for Temperature Variation insensitive circuit performance is, therefore, particularly attractive for low-power applications with relaxed speed requirements. A new design methodology based on threshold voltage optimization for achieving Temperature Variation insensitive circuit speed is also evaluated. The energy per cycle and the propagation delay at the supply and threshold voltages providing Temperature Variation insensitive circuit performance, minimum energy-delay product, and minimum energy are compared. Results indicate that low-power operation and Temperature Variation tolerance can be simultaneously achieved with the proposed techniques. © 2007 Elsevier Ltd. All rights reserved
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Voltage optimization for simultaneous energy efficiency and Temperature Variation resilience in CMOS circuits
Microelectronics Journal, 2007Co-Authors: R. Kumar, Volkan KursunAbstract:A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and Temperature Variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay Variations when the Temperature fluctuates are identified for a diverse set of circuits in 180 and 65nm CMOS technologies. Circuits display Temperature Variation insensitive propagation delay when operated at a supply voltage 44-47% lower than the nominal supply voltage (V"D"D=1.8V) in a 180nm CMOS technology. Similarly, the optimum supply voltages are 67-68% lower than the nominal supply voltage (V"D"D=1.0V) in a 65nm CMOS technology. At scaled supply voltages, integrated circuits consume lower power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for Temperature Variation insensitive circuit performance is, therefore, particularly attractive for low-power applications with relaxed speed requirements. A new design methodology based on threshold voltage optimization for achieving Temperature Variation insensitive circuit speed is also evaluated. The energy per cycle and the propagation delay at the supply and threshold voltages providing Temperature Variation insensitive circuit performance, minimum energy-delay product, and minimum energy are compared. Results indicate that low-power operation and Temperature Variation tolerance can be simultaneously achieved with the proposed techniques.
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Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology
2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006Co-Authors: R. Kumar, Volkan KursunAbstract:A design methodology based on optimizing the supply voltage for simultaneously achieving energy efficiency and Temperature Variation insensitive circuit performance is presented in this paper. Circuits exhibit Temperature Variation insensitive delay characteristics when operated at a supply voltage 67% to 68% lower than the nominal supply voltage. At scaled supply voltages, integrated circuits consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for Temperature Variation insensitive circuit performance is, therefore, particularly attractive for low power applications with relaxed speed requirements. The supply voltages that yield minimum energy and minimum energy-delay product are identified at two different Temperatures for circuits in a 65 nm CMOS technology. The energy and speed at the supply voltages providing Temperature Variation insensitive propagation delay, minimum energy, and minimum energy-delay product are compared. Results indicate that energy efficient integrated circuits with deeply scaled supply voltages can also be made insensitive to Temperature fluctuations by considering the Temperature dependence of speed in the supply voltage optimization process.
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Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison
2006 IEEE International SOC Conference, 2006Co-Authors: R. Kumar, Volkan KursunAbstract:In this paper, the supply and threshold voltage optimization techniques to achieve Temperature Variation insensitive circuit performance are compared. The speed and energy tradeoffs with the two optimization techniques are presented.
Nawaf H Saeid - One of the best experts on this subject based on the ideXlab platform.
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natural convection in porous cavity with sinusoidal bottom wall Temperature Variation
International Communications in Heat and Mass Transfer, 2005Co-Authors: Nawaf H SaeidAbstract:Abstract Numerical study of natural convection in a porous cavity is carried out in the present paper. Natural convection is induced when the bottom wall is heated and the top wall is cooled while the vertical walls are adiabatic. The heated wall is assumed to have spatial sinusoidal Temperature Variation about a constant mean value which is higher than the cold top wall Temperature. The non-dimensional governing equations are derived based on the Darcy model. The effects of the amplitude of the bottom wall Temperature Variation and the heat source length on the natural convection in the cavity are investigated for Rayleigh number range 20–500. It is found that the average Nusselt number increases when the length of the heat source or the amplitude of the Temperature Variation increases. It is observed that the heat transfer per unit area of the heat source decreases by increasing the length of the heated segment.
Bao Yang - One of the best experts on this subject based on the ideXlab platform.
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general characteristics of Temperature Variation in china during the last two millennia
Geophysical Research Letters, 2002Co-Authors: Bao Yang, Achim Braeuning, Kathleen R Johnson, Shi YafengAbstract:Three alternate China-wide Temperature composites covering the last 2000 years were established by combining multiple paleoclimate proxy records obtained from ice cores, tree rings, lake sediments and historical documents. Five periods of Temperature Variation can be identified: a warm stage in AD 0–240, a cold interval between AD 240 and 800, a return to warm conditions from AD 800–1400, including the Medieval Warm Period between AD 800–1100, the cool Little Ice Age period between 1400–1920, and the present warm stage since 1920. Regional Temperature Variation is found during AD 800–1100, when warm conditions occurred in Eastern China and in the northeastern Tibetan Plateau and in AD 1150–1380, when the southern Tibetan Plateau experienced a warm interval. In contrast, evidence for cool conditions during the LIA is more consistent among the proxy records. The Temperature reconstructions for China and the Northern Hemisphere show good agreement over the past millennium.
