The Experts below are selected from a list of 99 Experts worldwide ranked by ideXlab platform

Maciej Tyszka - One of the best experts on this subject based on the ideXlab platform.

  • Harmony Search for Self-configuration of Fault–Tolerant and Intelligent Grids
    2016
    Co-Authors: Jerzy Balicki, Waldemar Korłub, Jacek Paluszak, Maciej Tyszka
    Abstract:

    In this paper, harmony search algorithms have been proposed to self-configuration of intelligent grids for big data processing. Self-configuration of computer grids lies in the fact that new computer Nodes are automatically configured by software agents and then integrated into the grid. A Base Node works due to several configuration parameters that define some aspects of data communications and energy power consumption. We propose some optimization agents that are Based on harmony search to find a suboptimal configuration of fault–tolerant grids processing big data. Criteria such as probability that all tasks meet their deadlines and also a reliability of grid are considered. Finally, some experimental results have been considered.

  • CISIM - Harmony Search for Self-configuration of Fault–Tolerant and Intelligent Grids
    Computer Information Systems and Industrial Management, 2016
    Co-Authors: Jerzy Balicki, Waldemar Korłub, Jacek Paluszak, Maciej Tyszka
    Abstract:

    In this paper, harmony search algorithms have been proposed to self-configuration of intelligent grids for big data processing. Self-configuration of computer grids lies in the fact that new computer Nodes are automatically configured by software agents and then integrated into the grid. A Base Node works due to several configuration parameters that define some aspects of data communications and energy power consumption. We propose some optimization agents that are Based on harmony search to find a suboptimal configuration of fault–tolerant grids processing big data. Criteria such as probability that all tasks meet their deadlines and also a reliability of grid are considered. Finally, some experimental results have been considered.

Chul Soon Park - One of the best experts on this subject based on the ideXlab platform.

  • pcs w cdma dual band mmic power amplifier with a newly proposed linearizing bias circuit
    IEEE Journal of Solid-state Circuits, 2002
    Co-Authors: Y S Noh, Chul Soon Park
    Abstract:

    A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the Base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the Base Node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the Base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.

  • linearized high efficient hbt power amplifier module for l band application
    IEEE Gallium Arsenide Integrated Circuit Symposium, 2001
    Co-Authors: Y S Noh, T W Lee, Chul Soon Park
    Abstract:

    A new on-chip linearizer that is applicable to L-band application is proposed. It is composed of Base-emitter diode of the active bias transistor and a capacitor for RF signal shorting to the Base Node of the active bias transistor, which improves the gain compression and phase advance of the power amplifier with no additional DC power consumption, and has negligible signal loss with almost no increase in die area. The linearizer increases the 1 dB gain compression point by 18 dB and phase distortion by 16.49/spl deg/ while maintaining the Base bias voltage of the power amplifier. A PCS and W-CDMA dual band power amplifier with single input, single output, and no switch for band selection is implemented by designing the amplifier with broadband characteristics, and exhibits an output power of 28.97(28.3) dBm, PAE of 44.7(37.4)%, and adjacent channel power ratio (ACPR) of -41(-45) dBc at the output power of 28(28) dBm under 3.0 V operation voltage for PCS(W-CDMA) applications.

Jerzy Balicki - One of the best experts on this subject based on the ideXlab platform.

  • Harmony Search for Self-configuration of Fault–Tolerant and Intelligent Grids
    2016
    Co-Authors: Jerzy Balicki, Waldemar Korłub, Jacek Paluszak, Maciej Tyszka
    Abstract:

    In this paper, harmony search algorithms have been proposed to self-configuration of intelligent grids for big data processing. Self-configuration of computer grids lies in the fact that new computer Nodes are automatically configured by software agents and then integrated into the grid. A Base Node works due to several configuration parameters that define some aspects of data communications and energy power consumption. We propose some optimization agents that are Based on harmony search to find a suboptimal configuration of fault–tolerant grids processing big data. Criteria such as probability that all tasks meet their deadlines and also a reliability of grid are considered. Finally, some experimental results have been considered.

  • CISIM - Harmony Search for Self-configuration of Fault–Tolerant and Intelligent Grids
    Computer Information Systems and Industrial Management, 2016
    Co-Authors: Jerzy Balicki, Waldemar Korłub, Jacek Paluszak, Maciej Tyszka
    Abstract:

    In this paper, harmony search algorithms have been proposed to self-configuration of intelligent grids for big data processing. Self-configuration of computer grids lies in the fact that new computer Nodes are automatically configured by software agents and then integrated into the grid. A Base Node works due to several configuration parameters that define some aspects of data communications and energy power consumption. We propose some optimization agents that are Based on harmony search to find a suboptimal configuration of fault–tolerant grids processing big data. Criteria such as probability that all tasks meet their deadlines and also a reliability of grid are considered. Finally, some experimental results have been considered.

Y S Noh - One of the best experts on this subject based on the ideXlab platform.

  • pcs w cdma dual band mmic power amplifier with a newly proposed linearizing bias circuit
    IEEE Journal of Solid-state Circuits, 2002
    Co-Authors: Y S Noh, Chul Soon Park
    Abstract:

    A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the Base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the Base Node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the Base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.

  • linearized high efficient hbt power amplifier module for l band application
    IEEE Gallium Arsenide Integrated Circuit Symposium, 2001
    Co-Authors: Y S Noh, T W Lee, Chul Soon Park
    Abstract:

    A new on-chip linearizer that is applicable to L-band application is proposed. It is composed of Base-emitter diode of the active bias transistor and a capacitor for RF signal shorting to the Base Node of the active bias transistor, which improves the gain compression and phase advance of the power amplifier with no additional DC power consumption, and has negligible signal loss with almost no increase in die area. The linearizer increases the 1 dB gain compression point by 18 dB and phase distortion by 16.49/spl deg/ while maintaining the Base bias voltage of the power amplifier. A PCS and W-CDMA dual band power amplifier with single input, single output, and no switch for band selection is implemented by designing the amplifier with broadband characteristics, and exhibits an output power of 28.97(28.3) dBm, PAE of 44.7(37.4)%, and adjacent channel power ratio (ACPR) of -41(-45) dBc at the output power of 28(28) dBm under 3.0 V operation voltage for PCS(W-CDMA) applications.

Katsuhiko Hieda - One of the best experts on this subject based on the ideXlab platform.

  • BiCMOS circuit technology for high-speed DRAMs
    IEEE Journal of Solid-state Circuits, 1993
    Co-Authors: Shigeyoshi Watanabe, Koji Sakui, Tsuneaki Fuse, Takahiko Hara, Seiichi Aritome, Katsuhiko Hieda
    Abstract:

    A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the Base Node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed. >