The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
M Katakura - One of the best experts on this subject based on the ideXlab platform.
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a complete single chip gps receiver with 1 6 v 24 mw radio in 0 18 spl mu m cmos
IEEE Journal of Solid-state Circuits, 2004Co-Authors: T Kadoyama, N Suzuki, N Sasho, H Iizuka, I Nagase, H Usukubo, M KatakuraAbstract:We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost, and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a Baseband Processor, such as SoC, in a GPS receiver. The GPS chip, with a total size of 6.3 mm /spl times/ 6.3 mm, contains a 2.3 mm /spl times/ 2.0 mm radio part, including RF front end, phase-locked loops, IF functions, and 500 K gates of Baseband logic, including mask ROM, SRAM, and dual port SRAM . It is fabricated using 0.18-/spl mu/m CMOS technology with a MIM capacitor and operates from a 1.6-2.0-V power supply. Experimental results show a very low power consumption of, typically, 57 mW for a fully functional chip including Baseband, and a high sensitivity of -152dBm. Through countermeasures against substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external low-noise amplifier.
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a complete single chip gps receiver with 1 6 v 24 mw radio in 0 18 spl mu m cmos
Symposium on VLSI Circuits, 2003Co-Authors: T Kadoyama, N Suzuki, N Sasho, H Iizuka, I Nagase, H Usukubo, M KatakuraAbstract:We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a Baseband Processor, such as SoC., in a GPS receiver. The GPS chip, with a total size of 6.4/spl times/6.4 mm, contains a 2.3/spl times/2.0 mm radio part, including RF front end, PLLs, IF functions, and 500 K gates of Baseband logic, including mask ROM, SRAM and Dual Port SRAM. It's fabricated using 0.18-/spl mu/m CMOS Technology with a MIM option and operates from a 1.6 to 2.0-V power supply. Experimental results show a very low power consumption of, typically, 57-mW for a fully functional chip including Baseband, and a high sensitivity of -150 dBm. Through countermeasures for substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external LNA.
Sofie Pollin - One of the best experts on this subject based on the ideXlab platform.
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exploration of lattice reduction aided soft output mimo detection on a dlp ilp Baseband Processor
IEEE Transactions on Signal Processing, 2013Co-Authors: Ubaid Ahmad, Raf Appeltans, Hoang Duy Nguyen, Amir Amin, Antoine Dejonghe, Liesbet Van Der Perre, Rudy Lauwereins, Sofie PollinAbstract:Lattice Reduction aided soft output MIMO detectors (LR-SOMD) have been demonstrated to offer a promising gain. This work explores the potential of implementing a LR-SOMD on a parallel programmable Baseband Processor. In this paper, first a LR algorithm called the Data Regularized Parallel Lattice Reduction algorithm (DRP-LR) is proposed. Afterwards, a low-complexity LR-SOMD, Radius Constrained Multi-Tree Selective Spanning (RC-MTSS) is presented. RC-MTSS uses a novel multiple-tree search approach for LR-SOMD, while combining the benefits of Sphere Detection (SD) and Selective Spanning with Fast Enumeration (SSFE). A fixed complexity LR-SOMD, Multi-Tree Selective Spanning (MTSS) is also proposed for implementation. Both the algorithms, DRP-LR and MTSS, are enabled to exploit data level parallelism (DLP) and instruction level parallelism (ILP). In order to evaluate performance, the proposed DRP-LR and MTSS are implemented on the ADRES Baseband Processor for a 4 × 4 LTE system using QAM-64. DRP-LR achieves an average throughput of 33.33 M LR per second, which is comparable to recently reported ASIC implementations, while MTSS shows an average throughput of 730 Mbps on the same Processor. To the best of authors' knowledge, this is the first reported implementation of a LR-SOMD algorithm on a parallel programmable Baseband Processor.
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exploration of full hd media decoding on a software defined radio Baseband Processor
IEEE Transactions on Signal Processing, 2013Co-Authors: Chen Mei, Amir Amin, Antoine Dejonghe, Liesbet Van Der Perre, Peng Cao, Jun Yang, Longxing Shi, Sofie PollinAbstract:Recently, various specialized Software Defined Radio (SDR) Baseband Processors have been proposed for meeting the high performance and programmability requirements for emerging wireless communication applications. In order to support high throughput wireless communication, the SDR Baseband Processors typically employ many parallel computation elements, which may also be used for performing other signal processing applications. This paper explores the feasibility of performing complex media processing on such SDR Baseband Processors. Specifically, the full HD 1080p state-of-the-art H.264/AVC media decoding has been implemented onto a recent version of the ADRES based SDR Baseband Processor. Since the Processor was originally designed exclusively for wireless Baseband applications, algorithm and architecture co-optimizations are required to make the goal feasible. Following algorithm analysis, the computationally dominant tasks of the H.264/AVC, including the motion compensation, the intra prediction, the inverse integer transform, and the deblocking filter, have been selected to be mapped onto the ADRES. The experimental results show that, with limited architectural extensions, the ADRES based Baseband Processor achieves competitive performance efficiency, even compared with several Processors that are specifically optimized for the media decoding application.
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scalable block based parallel lattice reduction algorithm for an sdr Baseband Processor
International Conference on Communications, 2011Co-Authors: Ubaid Ahmad, Amir Amin, Liesbet Van Der Perre, Sofie Pollin, Francky CatthoorAbstract:Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. In this paper the Scalable Block-based Parallel LR algorithm (SBP-LR) is proposed and optimized for parallel programmable Baseband architectures offering ILP and DLP features. In our algorithm, architecture-friendliness is explicitly introduced from the very beginning of the algorithm/architecture co-design flow. In this context, abundant vector-parallelism is enabled with highly-regular and deterministic data-flow. Hence, SBP-LR can be easily parallelized and efficiently mapped on Software Defined Radio (SDR) Baseband architectures. The proposed algorithm has been implemented on ADRES and is evaluated in the context of 3GPP LTE. Most of the previously reported algorithms are implemented for ASIC or FPGA. However, to the best of author's knowledge, this is the first reported LR algorithm explicitly optimized for a Coarse Grain Reconfigurable Array (CGRA) Processor like ADRES.
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hybrid lattice reduction algorithm and its implementation on an sdr Baseband Processor for lte
European Signal Processing Conference, 2011Co-Authors: Ubaid Ahmad, Amir Amin, Liesbet Van Der Perre, Sofie Pollin, Rudy LauwereinsAbstract:Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. This paper proposes a Hybrid LR algorithm (HLR), which is a scalable LR algorithm. HLR is specifically designed and optimised to exploit ILP and DLP features offered by parallel programmable Baseband architectures. Abundant vector-parallelism in HLR is enabled with highly-regular and deterministic data-flow. Hence, HLR can be easily parallelized and efficiently mapped on Software Defined Radio (SDR) Baseband architectures. HLR can be adapted to operate in two different modes to achieve the best performance/cycle trade-off, which is highly desirable for SDR Baseband processing. The proposed algorithm has been evaluated in the context of 3GPP-LTE and implemented on ADRES which is a Coarse Grain Reconfigurable Array (CGRA) Processor. Most of the previously reported implementations of LR algorithms are for ASIC or FPGA. However, to the best of author's knowledge, this is the first reported LR algorithm explicitly designed and optimized, to have a scalable and adaptive implementation for a CGRA Processor like ADRES. The reported implementation of HLR can achieve gains of up to 12 dB compared to ZF for MIMO detection.
Yong H. Lee - One of the best experts on this subject based on the ideXlab platform.
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MSE-Based Hybrid RF/Baseband Processing for Millimeter-Wave Communication Systems in MIMO Interference Channels
IEEE Transactions on Vehicular Technology, 2015Co-Authors: Min-hyun Kim, Yong H. LeeAbstract:We consider the design of a hybrid multiple-input multiple-output (MIMO) Processor consisting of a radio frequency (RF) beamformer and a Baseband MIMO Processor for millimeter-wave communications over multiuser interference channels. Sparse approximation problems are formulated to design hybrid MIMO Processors approximating the minimum-mean-square-error transmit/receive Processors in MIMO interference channels. They are solved by orthogonal-matching-pursuit-based algorithms that successively select RF beamforming vectors from a set of candidate vectors and optimize the corresponding Baseband Processor in the least squares sense. It is shown that various beamformers can be designed by considering different types of candidate vector sets. Simulation results demonstrate the advantage of the proposed design over the conventional method that designs the Baseband Processor after steering the RF beams.
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AF relaying for millimeter wave communication systems with hybrid RF/Baseband MIMO processing
2014 IEEE International Conference on Communications ICC 2014, 2014Co-Authors: Junho Lee, Yong H. LeeAbstract:Due to the high cost and power consumption of radio frequency (RF) chains, millimeter wave (mm-wave) communication systems equipped with large antenna arrays typically employ less RF chains than the antenna elements. This leads to the use of a hybrid MIMO Processor consisting of a RF beamformer and a Baseband MIMO Processor in mm-wave communications. In this paper, we consider amplify-and-forward (AF) relay-assisted mm-wave systems with the hybrid MIMO Processors over frequency-selective channels. We develop an iterative algorithm for jointly designing the receive/transmit (Rx/Tx) RF/Baseband Processors of the relay based on the orthogonal matching pursuit (OMP) algorithm for sparse approximation, while assuming orthogonal frequency division multiplexing (OFDM) signaling. Simulation results show that the proposed method outperforms the conventional method that designs the Baseband Processor after steering the RF beams.
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Exploiting spatial sparsity for estimating channels of hybrid MIMO systems in millimeter wave communications
2014 IEEE Global Communications Conference GLOBECOM 2014, 2014Co-Authors: Junho Lee, Gye Tae Gil, Yong H. LeeAbstract:Hybrid multiple input multiple output (MIMO) systems consist of an analog beamformer with large antenna arrays followed by a digital MIMO Processor. Channel estimation for hybrid MIMO systems in millimeter wave (mm-wave) communications is challenging because of the large antenna array and the low signal-to-noise ratio (SNR) before beamforming. In this paper, we propose an open-loop channel estimator for mm-wave hybrid MIMO systems exploiting the sparse nature of mm-wave channels. A sparse signal recovery problem is formulated for channel estimation and solved by the orthogonal matching pursuit (OMP) based methods. A modification of the OMP algorithm, called the multi-grid (MG) OMP, is proposed. It is shown that the MG-OMP can significantly reduce the computational load of the OMP method. A process for designing the training beams is also developed. Specifically, given the analog training beams the Baseband Processor for beam training is designed. Simulation results demonstrate the advantage of the OMP based methods over the conventional least squares (LS) method and the efficiency of the MG-OMP over the original OMP.
Trevor Mudge - One of the best experts on this subject based on the ideXlab platform.
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A low power software-defined-radio Baseband Processor for the Internet of Things
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016Co-Authors: Yajing Chen, Trevor Mudge, Hun-seok Kim, David Blaauw, Ronald G. DreslinskiAbstract:In this paper, we define a configurable Software Defined Radio (SDR) Baseband Processor design for the Internet of Things (IoT). We analyzed the fundamental algorithms in communications systems on IoT devices to enable a microarchitecture design that supports many IoT standards and custom nonstandard communications. Based on this analysis, we propose a custom SIMD execution model coupled with a scalar unit. We introduce several architectural optimizations to this design: streaming registers, variable bit width datapath, dedicated ALUs for critical kernels, and an optimized flexible reduction network. We employ voltage scaling and clock gating to further reduce the power, while more than a 100% time margin has been reserved for reliable operation in the near-threshold region. Together our architectural enhancements lead to a 71× power reduction compared to a classic general purpose SDR SIMD architecture. Our IoT SDR datapath has sub-mW power consumption based on SPICE simulation, and is placed and routed to fit within an area of 0.074mm2 in a 28nm process. We implemented several essential elementary signal processing kernels and combined them to demonstrate two end-to-end upper bound systems, 802.15.4-OQPSK and Bluetooth Low Energy. Our full SDR Baseband system consists of a configurable SIMD with a control plane MCU and memory. For comparison, the best commercial wireless transceiver consumes 23.8mW for the entire wireless system (digital/RF/ analog). We show that our digital system power is below 2mW, in other words only 8% of the total system power. The wireless system is dominated by RF/analog power comsumption, thus the price of flexibility that SDR affords is small. We believe this work is unique in demonstrating the value of Baseband SDR in the low power IoT domain.
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From SODA to scotch: The evolution of a wireless Baseband Processor
Proceedings of the Annual International Symposium on Microarchitecture MICRO, 2008Co-Authors: Mark Woh, Richard Bruce, Danny Kershaw, Sangwon Seo, Alastair Reid, Scott Mahlke, Chaitali Chakrabarti, Trevor Mudge, Yuan Lin, Mladen WilderAbstract:With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only Baseband processing solutions to adapt to the rapidly changing wireless communication landscape. Software Defined Radio (SDR) promises to deliver a cost effective and flexible solution by implementing a wide variety of wireless protocols in software. In previous work, a fully programmable multicore architecture, SODA, was proposed that was able to meet the real-time requirements of 3G wireless protocols. SODA consists of one ARM control Processor and four wide single instruction multiple data (SIMD) processing elements. Each processing element consists of a scalar and a wide 512-bit 32-lane SIMD datapath. A commercial prototype based on the SODA architecture, Ardbeg (named after a brand of Scotch Whisky), has been developed. In this paper, we present the architectural evolution of going from a research design to a commercial prototype, including the goals, tradeoffs, and final design choices. Ardbeg’s redesign process can be grouped into the fol- lowing three major areas: optimizing the wide SIMD dat- apath, providing long instruction word (LIW) support for SIMD operations, and adding application-specific hardware accelerators. Because SODA was originally designed with 180nm technology, the wide SIMD datapath is re-optimized in Ardbeg for 90nm technology. This includes re-evaluating the most efficient SIMD width, designing a wider SIMD shuffle network, and implementing faster SIMD arithmetic units. Ardbeg also provides modest LIW support by allowing two SIMD operations to issue in the same cycle. This LIW execution supports SDR algorithms’ most common parallel SIMD execution patterns with minimal hardware overhead. A viable commercial SDR solution must be competitive with existing ASIC solutions. Therefore, algorithm-specific hardware is added for performance bottleneck algorithms while still maintaining enough flexibility to support multiple wireless protocols. The combination of these architectural improvements allows Ardbeg to achieve 1.5-7x speedup over SODA across multiple wireless algorithms while consuming less power.
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a Baseband Processor for software defined radio terminals
2007Co-Authors: Trevor Mudge, Hyunseok LeeAbstract:Software defined radio (SDR) is a technical effort to use programmable hardware in wireless communication systems so that various protocols can be easily supported by software. However, using programmable hardware for SDR terminals has been unachievable because of their tight power budget and high demand on computation capability. The main theme of this thesis is to design a power efficient programmable Baseband Processor for the SDR. This thesis analyzed most contemporary wireless communication protocols both in system and algorithm levels. System level analysis is to see the interactions between algorithms and the algorithm level analysis is to investigate the computation patterns of the algorithms comprising Baseband operations. Based on the characterization results, this thesis proposes chip multiProcessor architecture, whose PEs have both parallel and scalar datapaths. MultiProcessor architecture is proposed to exploit the algorithm level parallelism. Both the parallel and scalar datapaths are used because Baseband processing is a combination of parallelizable and scalar computations. For additional enhancements, three novel schemes are applied to the SIMD style parallel datapath: macro instructions, macro pipelining, and the staggered execution of computation units. Macro instruction is to combine several primitive instructions into one. It reduces system power by eliminating unnecessary register accesses. The macro pipelining is to form a pipeline by cascading hardware blocks for common macro operations. It enhances system throughput by concurrently executing the macro operations. The staggered execution is to shift the operation timing of computation units of the parallel datapath. It improves system throughput and power efficiency by replacing complex N × N crossbar switches with simple N × 1 switches. The power efficiency of the proposed architecture is evaluated through a Verilog model and commercial tools. The proposed architecture consumes only 150 mW while providing W-CDMA 2Mbps packet data service. The contributions of this thesis are to analyze the characteristics of Baseband operations from the perspective of architecture and to adapt the three novel schemes for system enhancement.
Anantha P Chandrakasan - One of the best experts on this subject based on the ideXlab platform.
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a 0 4 v uwb Baseband Processor
International Symposium on Low Power Electronics and Design, 2007Co-Authors: Vivienne Sze, Anantha P ChandrakasanAbstract:A 0.4-V UWB digital Baseband Processor has been fabricated in a standard-VT 90-nm CMOS technology. The base-band Processor operates at an ultra-low supply voltage to reduce energy consumption and utilizes a highly parallelized architecture to meet throughput constraints. While ultra-low voltage operation is usually limited to low energy, low performance applications, this work examines how it can be applied to low energy, high performance applications. Measured results for a 20-pJ/bit 100-Mbps UWB Baseband Processor are presented. Architectural techniques and design methodologies for reducing additional complexity due to parallelism are discussed.
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an energy efficient sub threshold Baseband Processor architecture for pulsed ultra wideband communications
International Conference on Acoustics Speech and Signal Processing, 2006Co-Authors: Vivienne Sze, R Blazquez, M Bhardwaj, Anantha P ChandrakasanAbstract:This paper describes how parallelism in the digital Baseband Processor can reduce the energy required to receive ultra-wideband (UWB) packets. The supply voltage of the digital Baseband is lowered so that the correlator operates near its minimum energy point resulting in a 68% energy reduction across the entire Baseband. This optimum supply voltage occurs below the threshold voltage, placing the circuit in the sub-threshold region. The correlator and the rest of the Baseband must be parallelized to maintain throughput at this reduced voltage. While sub-threshold operation is traditionally used for low energy, low frequency applications such as wrist-watches, this paper examines how sub-threshold operation can be applied to low energy, high performance applications. The correlators are further parallelized for a 31x reduction in the synchronization time, which along with duty-cycling, lowers the energy per packet by 43% for a 500 byte packet. Simulation results for a 100 Mbps UWB Baseband Processor are described
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a Baseband Processor for impulse ultra wideband communications
Custom Integrated Circuits Conference, 2005Co-Authors: R Blazquez, P P Newaskar, F S Lee, Anantha P ChandrakasanAbstract:This paper presents a Baseband Processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 μs. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The Baseband Processor and ADC were implemented on the same 0.18-μm CMOS die at 1.8 V as part of a complete Baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.
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a Baseband Processor for pulsed ultra wideband signals
Custom Integrated Circuits Conference, 2004Co-Authors: R Blazquez, P P Newaskar, F S Lee, Anantha P ChandrakasanAbstract:This paper presents a Baseband Processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 /spl mu/s. The Baseband Processor was implemented in the same 0.18 /spl mu/m CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated.