The Experts below are selected from a list of 15666 Experts worldwide ranked by ideXlab platform

Mohammad Tehranipoor - One of the best experts on this subject based on the ideXlab platform.

  • ron an on chip ring oscillator network for hardware trojan detection
    Design Automation and Test in Europe, 2011
    Co-Authors: Xuehui Zhang, Mohammad Tehranipoor
    Abstract:

    Integrated Circuits (ICs) are becoming increasingly vulnerable to malicious alterations, referred to as hardware Trojans. Detection of these inclusions is of utmost importance, as they may potentially be inserted into ICs bound for military, financial, or other critical applications. A novel on-chip structure including a ring oscillator network (RON), distributed across the entire chip, is proposed to verify whether the chip is Trojan-free. This structure effectively eliminates the issue of measurement noise, localizes the measurement of dynamic power, and additionally compensates for the impact of process variations. Combined with statistical data analysis, the separation of process variations from the Trojan contribution to the Circuit's transient power is made possible. Simulation results featuring Trojans inserted into a Benchmark Circuit using 90nm technology and experimental results on Xilinx Spartan-3E FPGA demonstrate the efficiency and scalability of the RON architecture for Trojan detection.

Laxmi Kumre - One of the best experts on this subject based on the ideXlab platform.

  • Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
    Circuits Systems and Signal Processing, 2020
    Co-Authors: Trapti Sharma, Laxmi Kumre
    Abstract:

    This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced Circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the Benchmark Circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and Circuit level is achieved through the optimized designs of various adder and multiplier Circuits.

  • Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
    Circuits Systems and Signal Processing, 2019
    Co-Authors: Trapti Sharma, Laxmi Kumre
    Abstract:

    This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced Circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the Benchmark Circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and Circuit level is achieved through the optimized designs of various adder and multiplier Circuits.

Xuehui Zhang - One of the best experts on this subject based on the ideXlab platform.

  • ron an on chip ring oscillator network for hardware trojan detection
    Design Automation and Test in Europe, 2011
    Co-Authors: Xuehui Zhang, Mohammad Tehranipoor
    Abstract:

    Integrated Circuits (ICs) are becoming increasingly vulnerable to malicious alterations, referred to as hardware Trojans. Detection of these inclusions is of utmost importance, as they may potentially be inserted into ICs bound for military, financial, or other critical applications. A novel on-chip structure including a ring oscillator network (RON), distributed across the entire chip, is proposed to verify whether the chip is Trojan-free. This structure effectively eliminates the issue of measurement noise, localizes the measurement of dynamic power, and additionally compensates for the impact of process variations. Combined with statistical data analysis, the separation of process variations from the Trojan contribution to the Circuit's transient power is made possible. Simulation results featuring Trojans inserted into a Benchmark Circuit using 90nm technology and experimental results on Xilinx Spartan-3E FPGA demonstrate the efficiency and scalability of the RON architecture for Trojan detection.

Trapti Sharma - One of the best experts on this subject based on the ideXlab platform.

  • Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
    Circuits Systems and Signal Processing, 2020
    Co-Authors: Trapti Sharma, Laxmi Kumre
    Abstract:

    This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced Circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the Benchmark Circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and Circuit level is achieved through the optimized designs of various adder and multiplier Circuits.

  • Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
    Circuits Systems and Signal Processing, 2019
    Co-Authors: Trapti Sharma, Laxmi Kumre
    Abstract:

    This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced Circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the Benchmark Circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and Circuit level is achieved through the optimized designs of various adder and multiplier Circuits.

Philippe Matherat - One of the best experts on this subject based on the ideXlab platform.

  • ICECS - A dual threshold voltage technique for glitch minimization
    2012 19th IEEE International Conference on Electronics Circuits and Systems (ICECS 2012), 2012
    Co-Authors: Mariem Slimani, Philippe Matherat, Y. Mathieu
    Abstract:

    We propose to use dual-threshold voltage (dual-Vth) assignment for glitch reduction. We present a heuristic algorithm address this problem. Experimental results on 6 ISCAS85 Benchmark Circuits implemented in a 65 nm industrial low power CMOS process report more than 16% of glitch reduction on average, and up to 41% for C432 Benchmark Circuit. To further minimize glitches, we propose to unify gate-sizing and dual-Vth techniques into a single optimization process. Results show an improvement of 10% on average compared to the conventional gate-sizing method. Spice simulations of C432 Benchmark Circuit report more than 27% and 48% total energy reduction by means the proposed dual-Vth and dual-Vth/gate-sizing algorithm, respectively.

  • Multiple Threshold Voltage for Glitch Power Reduction
    2011
    Co-Authors: Mariem Slimani, Philippe Matherat
    Abstract:

    We address the problem of Circuit-level design for low power. We describe a new method for glitch power reduction based on threshold voltage adjustment. The proposed method achieves both dynamic and leakage power reductions. We develop an optimization algorithm that transforms the Circuit netlist in an optimized one achieving glitch energy reductions without affecting the overall Circuit delay requirement. Applying the algorithm to C17 Benchmark Circuit implemented in a 65 nm industrial Low Power CMOS process, we have achieved 14% of total energy savings and 78% of leakage energy savings at the expense of just 5% of delay increase.