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Kumar Prasannajit Pradhan - One of the best experts on this subject based on the ideXlab platform.

  • ZTC Bias Point of advanced fin based device: The importance and exploration
    Facta universitatis - series: Electronics and Energetics, 2015
    Co-Authors: Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu
    Abstract:

    The present understanding of this work is about to evaluate and resolve the temperature compensation Point ( TCP ) or zero temperature coefficient ( ZTC ) Point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0 C to 225 0 C is reviewed to extend the benchmark of device scalability. The impact of fin height ( H Fin ), fin width ( W Fin ), and temperature ( T ) on immense performance metrics including on-off ratio ( I on / I off ), transconductance ( g m ), gain ( A V ), cut-off frequency ( f T ), static power dissipation ( P D ), energy ( E ), energy delay product (EDP), and sweet spot ( g m f T / I D ) of the FinFET is successfully carried out by commercially available TCAD simulator Sentaurus TM from Synopsis Inc.

  • Zero temperature-coefficient Bias Point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges
    Materials Science in Semiconductor Processing, 2015
    Co-Authors: Prasanna Kumar Sahu, Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan
    Abstract:

    Abstract This paper is a unique attempt to identify the zero-temperature-coefficient ( ZTC ) Point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400 K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a Biasing Point i.e. ZTC Bias Point, where the device parameters become independent of temperature. The impact of operating temperature ( T ) on various performance metrics like on current ( I on ), off current ( I off ), on-off current ratio ( I on /I off ), transconductance ( g m ), output conductance ( g d ), intrinsic gain ( A V ) and cut off frequency ( f T ) is also subjected to extensive analysis. The variation of ZTC Point for transconductance ( Z T C g m ) and drain current ( Z T C I D S ) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

  • RESOLVING THE Bias Point FOR WIDE RANGE OF TEMPERATURE APPLICATIONS IN HIGH-K/METAL GATE
    2014
    Co-Authors: Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu
    Abstract:

    This article investigates the Zero-Temperature-Coefficient (ZTC) Bias Point and its associated performance metrics of a High-k Metal Gate (HKMG) DG-MOSFET in nanoscale. The ZTC Bias Point is defined as the Point at which the device parameters are independent of temperature. The discussion includes sub threshold slope (SS), drain induced barrier lowering (DIBL), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd) and intrinsic gain (AV). From the results, it is confirmed that there are two different ZTC Bias Points, one for IDS (ZTCIDS) and the other for gm (ZTCgm). The Points are obtained as: ZTCIDS=0.552 V and ZTCgm =0.410 V, which will open important opportunities in analog circuit design for wide range of temperature applications.

K.r. Voisine - One of the best experts on this subject based on the ideXlab platform.

  • Bias Point thermal shift growth in Z-cut LiNbO/sub 3/ Modulators
    IEEE Photonics Technology Letters, 2005
    Co-Authors: H. Nagata, A. Finch, K.r. Voisine
    Abstract:

    Growth of a Bias Point thermal shift induced by dc Bias in z-cut LiNbO/sub 3/ optical intensity modulators is quantitatively discussed from the standPoint of its impact on field service. During 20 years of device operation under a worst-case dc Bias condition, the thermal shift slope grows almost symmetrically with respect to a Bias polarity. An initial small thermal shift of around /spl plusmn/7 mV//spl deg/C (3/spl sigma/ distribution bounds) increases continuously over time with Biased operation at 55/spl deg/C and approaches /spl plusmn/70 mV//spl deg/C after 20 years. This increased temperature sensitivity would generate approximately a 2-V Bias Point shift toward the Bias rail when modulator is exposed to temperature variation from 55/spl deg/C to 25/spl deg/C.

  • DC-Voltage-induced thermal shift of Bias Point in LiNbO/sub 3/ optical Modulators
    IEEE Photonics Technology Letters, 2004
    Co-Authors: H. Nagata, N.f. O'brien, W.r. Bosenberg, G.l. Reiff, K.r. Voisine
    Abstract:

    Increasing thermal shift of a Bias Point is observed when dc voltage is applied to z-cut LiNbO/sub 3/ (LN) modulators having asymmetric design; whereas, stable thermal shift is observed in symmetric x-cut LN modulators. A growth of the thermal shift depends upon the amplitude, polarity, and duration of the applied voltage and constitutes a new criterion to reliability modeling of LN modulators.

Prasanna Kumar Sahu - One of the best experts on this subject based on the ideXlab platform.

  • ZTC Bias Point of advanced fin based device: The importance and exploration
    Facta universitatis - series: Electronics and Energetics, 2015
    Co-Authors: Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu
    Abstract:

    The present understanding of this work is about to evaluate and resolve the temperature compensation Point ( TCP ) or zero temperature coefficient ( ZTC ) Point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0 C to 225 0 C is reviewed to extend the benchmark of device scalability. The impact of fin height ( H Fin ), fin width ( W Fin ), and temperature ( T ) on immense performance metrics including on-off ratio ( I on / I off ), transconductance ( g m ), gain ( A V ), cut-off frequency ( f T ), static power dissipation ( P D ), energy ( E ), energy delay product (EDP), and sweet spot ( g m f T / I D ) of the FinFET is successfully carried out by commercially available TCAD simulator Sentaurus TM from Synopsis Inc.

  • Zero temperature-coefficient Bias Point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges
    Materials Science in Semiconductor Processing, 2015
    Co-Authors: Prasanna Kumar Sahu, Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan
    Abstract:

    Abstract This paper is a unique attempt to identify the zero-temperature-coefficient ( ZTC ) Point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400 K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a Biasing Point i.e. ZTC Bias Point, where the device parameters become independent of temperature. The impact of operating temperature ( T ) on various performance metrics like on current ( I on ), off current ( I off ), on-off current ratio ( I on /I off ), transconductance ( g m ), output conductance ( g d ), intrinsic gain ( A V ) and cut off frequency ( f T ) is also subjected to extensive analysis. The variation of ZTC Point for transconductance ( Z T C g m ) and drain current ( Z T C I D S ) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

  • RESOLVING THE Bias Point FOR WIDE RANGE OF TEMPERATURE APPLICATIONS IN HIGH-K/METAL GATE
    2014
    Co-Authors: Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu
    Abstract:

    This article investigates the Zero-Temperature-Coefficient (ZTC) Bias Point and its associated performance metrics of a High-k Metal Gate (HKMG) DG-MOSFET in nanoscale. The ZTC Bias Point is defined as the Point at which the device parameters are independent of temperature. The discussion includes sub threshold slope (SS), drain induced barrier lowering (DIBL), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd) and intrinsic gain (AV). From the results, it is confirmed that there are two different ZTC Bias Points, one for IDS (ZTCIDS) and the other for gm (ZTCgm). The Points are obtained as: ZTCIDS=0.552 V and ZTCgm =0.410 V, which will open important opportunities in analog circuit design for wide range of temperature applications.

H. Nagata - One of the best experts on this subject based on the ideXlab platform.

  • Bias Point thermal shift growth in Z-cut LiNbO/sub 3/ Modulators
    IEEE Photonics Technology Letters, 2005
    Co-Authors: H. Nagata, A. Finch, K.r. Voisine
    Abstract:

    Growth of a Bias Point thermal shift induced by dc Bias in z-cut LiNbO/sub 3/ optical intensity modulators is quantitatively discussed from the standPoint of its impact on field service. During 20 years of device operation under a worst-case dc Bias condition, the thermal shift slope grows almost symmetrically with respect to a Bias polarity. An initial small thermal shift of around /spl plusmn/7 mV//spl deg/C (3/spl sigma/ distribution bounds) increases continuously over time with Biased operation at 55/spl deg/C and approaches /spl plusmn/70 mV//spl deg/C after 20 years. This increased temperature sensitivity would generate approximately a 2-V Bias Point shift toward the Bias rail when modulator is exposed to temperature variation from 55/spl deg/C to 25/spl deg/C.

  • DC-Voltage-induced thermal shift of Bias Point in LiNbO/sub 3/ optical Modulators
    IEEE Photonics Technology Letters, 2004
    Co-Authors: H. Nagata, N.f. O'brien, W.r. Bosenberg, G.l. Reiff, K.r. Voisine
    Abstract:

    Increasing thermal shift of a Bias Point is observed when dc voltage is applied to z-cut LiNbO/sub 3/ (LN) modulators having asymmetric design; whereas, stable thermal shift is observed in symmetric x-cut LN modulators. A growth of the thermal shift depends upon the amplitude, polarity, and duration of the applied voltage and constitutes a new criterion to reliability modeling of LN modulators.

Sushanta Kumar Mohapatra - One of the best experts on this subject based on the ideXlab platform.

  • ZTC Bias Point of advanced fin based device: The importance and exploration
    Facta universitatis - series: Electronics and Energetics, 2015
    Co-Authors: Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu
    Abstract:

    The present understanding of this work is about to evaluate and resolve the temperature compensation Point ( TCP ) or zero temperature coefficient ( ZTC ) Point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0 C to 225 0 C is reviewed to extend the benchmark of device scalability. The impact of fin height ( H Fin ), fin width ( W Fin ), and temperature ( T ) on immense performance metrics including on-off ratio ( I on / I off ), transconductance ( g m ), gain ( A V ), cut-off frequency ( f T ), static power dissipation ( P D ), energy ( E ), energy delay product (EDP), and sweet spot ( g m f T / I D ) of the FinFET is successfully carried out by commercially available TCAD simulator Sentaurus TM from Synopsis Inc.

  • Zero temperature-coefficient Bias Point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges
    Materials Science in Semiconductor Processing, 2015
    Co-Authors: Prasanna Kumar Sahu, Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan
    Abstract:

    Abstract This paper is a unique attempt to identify the zero-temperature-coefficient ( ZTC ) Point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400 K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a Biasing Point i.e. ZTC Bias Point, where the device parameters become independent of temperature. The impact of operating temperature ( T ) on various performance metrics like on current ( I on ), off current ( I off ), on-off current ratio ( I on /I off ), transconductance ( g m ), output conductance ( g d ), intrinsic gain ( A V ) and cut off frequency ( f T ) is also subjected to extensive analysis. The variation of ZTC Point for transconductance ( Z T C g m ) and drain current ( Z T C I D S ) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

  • RESOLVING THE Bias Point FOR WIDE RANGE OF TEMPERATURE APPLICATIONS IN HIGH-K/METAL GATE
    2014
    Co-Authors: Sushanta Kumar Mohapatra, Kumar Prasannajit Pradhan, Prasanna Kumar Sahu
    Abstract:

    This article investigates the Zero-Temperature-Coefficient (ZTC) Bias Point and its associated performance metrics of a High-k Metal Gate (HKMG) DG-MOSFET in nanoscale. The ZTC Bias Point is defined as the Point at which the device parameters are independent of temperature. The discussion includes sub threshold slope (SS), drain induced barrier lowering (DIBL), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd) and intrinsic gain (AV). From the results, it is confirmed that there are two different ZTC Bias Points, one for IDS (ZTCIDS) and the other for gm (ZTCgm). The Points are obtained as: ZTCIDS=0.552 V and ZTCgm =0.410 V, which will open important opportunities in analog circuit design for wide range of temperature applications.