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Binary Addition

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Minghua Che – One of the best experts on this subject based on the ideXlab platform.

  • basic regenerating code Binary Addition and shift for exact repair
    International Symposium on Information Theory, 2013
    Co-Authors: Hanxu Hou, Kenneth W Shum, Minghua Che

    Abstract:

    Regenerating code is a class of storage codes that achieve the optimal trade-off between storage capacity and repair bandwidth, which are two important performance metrics in data storage systems. However, existing constructions of regenerating codes rely on expensive computational operations such as finite field multiplication. The high coding and repair complexity limit their applications in large-scale practical storage systems. In this paper, we show that it is possible to achieve the full potential of regenerating codes with low computational complexity. In particular, we propose a new class of regenerating codes, called BASIC codes, that can achieve two specific points (i.e., minimum-bandwidth and minimum-storage regenerating points) on the storage and repair bandwidth trade-off curve, using only Binary Addition and shift operations in the coding and repair processes. Although in this paper we focus on constructing and analyzing BASIC codes for two specific exact-repair settings, our framework can be generalized to develop BASIC codes for more general exact- and functional-repair regenerating codes.

Mitchell A. Thornton – One of the best experts on this subject based on the ideXlab platform.

  • A digital-to-frequency converter using redundant signed Binary Addition
    2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009
    Co-Authors: Wickham Chen, Mitchell A. Thornton, Ping Gui

    Abstract:

    Redundant signed Binary Addition (RSBA) has been used to create high performance arithmetic circuits. This paper presents an accumulator-based digital-to-frequency (DFC) converter employing redundant signed Binary Addition (RSBA). RSBA is advantageous in that no carry propagation occurs resulting in constant delay regardless of operand word size. Utilizing RSBA in the proposed DFC resolves the performance bottleneck in the DFC’s conventional implementation and achieves extremely high frequency resolution. In Addition, a new RSBA-based 8∶1 Multiplexer is introduced for a complete RSBA implementation of the DFC. Experimental results show an increase of more than 3.5 times in the speed of the accumulator compared to the conventional implementation regardless of bit size of the adder.

  • Redundant signed Binary Addition based digital-to-frequency converter
    Electronics Letters, 2009
    Co-Authors: Wickham Chen, Mitchell A. Thornton, Ping Gui

    Abstract:

    An accumulator-based digital-to-frequency (DFC) converter employing redundant signed Binary Addition (RSBA) is presented. RSBA is advantageous in that no carry propagation occurs resulting in constant delay regardless of operand word size. Utilising RSBA in the proposed DFC resolves the performance bottleneck in the DFC’s conventional implementation and achieves extremely high frequency resolution. In Addition, a new RSBA-based 8∶1 multiplexer is introduced for a complete RSBA implementation of the DFC. Experimental results show an increase of more than 3.5 times in the speed of the accumulator compared to the conventional implementation regardless of bit size of the adder.

  • A signed Binary Addition circuit based on an alternative class of Addition tables
    Computers & Electrical Engineering, 2003
    Co-Authors: Mitchell A. Thornton

    Abstract:

    Abstract Redundant signed digit number systems have been used as a basis for the construction of fast arithmetic circuits for several years. In particular, Addition circuits with no carry-ripple effects have been developed using signed Binary arithmetic systems. This paper presents a general class of signed Binary Addition tables and provides a framework for constructing various tables. The existence of an entire class of tables provides a circuit designer with an Additional degree of freedom while developing Addition circuitry. The choice of the exact form of the Addition table can be based on the dominant desired characteristics of the resultant circuit. An example of a circuit derived for area minimization is presented and compared to another signed Binary Addition circuit that was previously published. Both circuits were optimized and mapped to 20 different CMOS cell libraries. The experimental results indicate an average decrease in area of 26% and an average decrease in dynamic power consumption of 29% with an average increase in delay of only 4.4%.

Stamatis Vassiliadis – One of the best experts on this subject based on the ideXlab platform.

  • Binary Addition based on single electron tunneling devices
    4th IEEE Conference on Nanotechnology 2004., 2004
    Co-Authors: C. Lageweg, Sorin Cotofana, Stamatis Vassiliadis

    Abstract:

    The ability to control the transport of individual electrons within single electron tunneling based circuits creates the conditions for implementing single electron encoded threshold logic gates. This paper investigates the implementation of Binary Addition based on such gates. We first propose implementations of full adder and 4-bit lookahead carry generator blocks and verify the designs by means of simulation. We then evaluate the area, delay, and power consumption of 16-bit and 64-bit ripple carry and carry-lookahead adders based on these blocks.

  • Capacitive threshold logic: a designer perspective
    CAS '99 Proceedings. 1999 International Semiconductor Conference (Cat. No.99TH8389), 1999
    Co-Authors: M. Padure, Sorin Cotofana, C. Dan, M. Bodea, Stamatis Vassiliadis

    Abstract:

    In this paper the authors present the main aspects of the Capacitive Threshold Logic (CTL) implementation. Several unique design problems typical to CTL design are presented using a design perspective. We also address the CTL implementation of /spl delta/-bit serial Binary Addition, performing a qualitative analysis of different implementation dependent approaches.

  • δ-Bit serial Binary Addition with linear threshold networks
    Journal of VLSI signal processing systems for signal image and video technology, 1996
    Co-Authors: Sorin Cotofana, Stamatis Vassiliadis

    Abstract:

    In this paper we investigate δ-bit serial Addition in the context of feed-forward linear threshold gate based networks. We show that two n -bit operands can be added in $$2\left\lceil {\sqrt n } \right\rceil $$ overall delay with a feed-forward network constructed with $$\left\lceil {\sqrt n } \right\rceil + 1$$ linear threshold gates and $$\frac{1}{2}\left( {5\left\lceil {\sqrt n } \right\rceil ^2 + 9\left\lceil {\sqrt n } \right\rceil } \right) + 2$$ latches. The maximum weight value is $$2^{\left\lceil {\sqrt n } \right\rceil } $$ and the maximum fan-in is $$3\left\lceil {\sqrt n } \right\rceil + 1$$ . We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that if the weight values are to be limited by a constant W , two n -bit operands can be added in $$\left[ {\log W} \right] + \tfrac{n}{{\left[ {\log W} \right]}}$$ overall delay with a feed-forward network that has the implementation cost [log W ]+1, in terms of linear threshold gates, $$\tfrac{1}{2}(5[\log W]^2 + 9[\log W]) + 2$$ in terms of latches and a maximum fan-in of 3[log W ]+1. We also prove that, if the fan-in values are to be limited by a constant F +1, two n -bit operands can be added in $$[\tfrac{F}{3}] + \tfrac{n}{{[\tfrac{F}{3}]}}$$ overall delay with a feed-forward network that has the implementation cost $$[\tfrac{F}{3}] + 1$$ , in terms of linear threshold gates, $$\tfrac{1}{2}(5[\tfrac{F}{3}]^2 + 9[\tfrac{F}{3}]) + 2$$ in terms of latches, and a maximum weight value of $$2^{[\tfrac{F}{3}]} $$ . An asymptotic bound of $$O(\tfrac{n}{{\log n}})$$ is derived for the Addition overall delay in the case that the weight values have to be linearly bounded, i.e., in the order of O(n) . The implementation cost in this case is in the order of O (log n ), in terms of linear threshold gates, and in the order of O (log^2 n ), in terms of latches. The maximum fan-in is in the order of O (log n ). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few Additional threshold gates, is also presented.