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Haroon Ahmed - One of the best experts on this subject based on the ideXlab platform.
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Nanosilicon for Single-Electron devices
Current Applied Physics, 2003Co-Authors: Hiroshi Mizuta, Zahid A. K. Durrani, Kazuo Nakazato, Y. Furuta, Toshio Kamiya, Y. T. Tan, Shuhei Amakawa, Haroon AhmedAbstract:This paper presents a brief overview of the physics of nanosilicon materials for Single-Electron device applications. We study how a nanosilicon grain and a discrete grain boundary work as a charging island and a tunnel barrier by using a point-contact transistor, which features an extremely short and narrow channel. Single-Electron charging phenomena are investigated by comparing asprepared devices and various oxidized devices. The optimization of grain and grain-boundary structural parameters is discussed for improving the Coulomb blockade characteristics and realizing room temperature device operation. � 2003 Published by Elsevier B.V. PACS: 81.07.Bc; 73.23.Hk; 85.35.Gv
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A memory cell with Single-Electron and metal-oxide-semiconductor transistor integration
Applied Physics Letters, 1999Co-Authors: Zahid A. K. Durrani, A. C. Irvine, Haroon Ahmed, Kazuo NakazatoAbstract:A Single-Electron transistor memory cell with metal-oxide-semiconductor field-effect transistor sensing has been fabricated in silicon-on-insulator material. The Single-Electron transistor, coupled to a memory node, is defined in the upper silicon layer. The memory node forms the gate of a metal-oxide-semiconductor field-effect transistor with its channel in the substrate silicon. At 4.2 K, there are two different states of the memory-node voltage, separated by the Single-Electron transistor Coulomb gap. These states are sensed at high-current output levels by the metal-oxide-semiconductor transistor. The metal-oxide-semiconductor transistor current also shows evidence of gate-dependent conductance oscillations in the coupled Single-Electron transistor.
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Single-Electron devices
Microelectronic Engineering, 1996Co-Authors: Haroon Ahmed, Kazuo NakazatoAbstract:The basic principles of Single-Electron charging effects are explained. The fabrication of island and tunnel junction structures in which Single-Electron devices can be realised is described. Structures based on metals, GaAs/AlGaAs heterointerfaces, @d-doped GaAs, silicon and silicon-on-insulator have been considered and some of the applications of Single Electronics such as the current standard and the Single Electron memory are described in this review.
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Single‐Electron memory
Journal of Applied Physics, 1994Co-Authors: Kazuo Nakazato, Richard J. Blaikie, Haroon AhmedAbstract:A Single‐Electron memory cell, in which one bit of information is represented by the excess or shortfall of a precise number of Electrons, is described. An experimental memory circuit was fabricated using side‐gated constrictions in δ‐doped GaAs, and the basic operation was confirmed from 30 mK up to liquid‐helium temperature of 4.2 K. This memory can store information for longer than several hours. The intrinsic Single‐Electron memory characteristics in a regime where cotunneling is neglected are investigated, and the overall characteristics are explained by a semiclassical model.
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Single-Electron memory
Electronics Letters, 1993Co-Authors: Kazuo Nakazato, Richard J. Blaikie, J. R. A. Cleaver, Haroon AhmedAbstract:A Single-Electron memory cell, in which one bit of information is represented by +n and −n Electron number states, is described. An experimental memory circuit for n ≃100 was fabricated and the basic operation was confirmed at a temperature of 30 mK. This structure can be modified to operate with n = 1.
Kazuo Nakazato - One of the best experts on this subject based on the ideXlab platform.
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Nanosilicon for Single-Electron devices
Current Applied Physics, 2003Co-Authors: Hiroshi Mizuta, Zahid A. K. Durrani, Kazuo Nakazato, Y. Furuta, Toshio Kamiya, Y. T. Tan, Shuhei Amakawa, Haroon AhmedAbstract:This paper presents a brief overview of the physics of nanosilicon materials for Single-Electron device applications. We study how a nanosilicon grain and a discrete grain boundary work as a charging island and a tunnel barrier by using a point-contact transistor, which features an extremely short and narrow channel. Single-Electron charging phenomena are investigated by comparing asprepared devices and various oxidized devices. The optimization of grain and grain-boundary structural parameters is discussed for improving the Coulomb blockade characteristics and realizing room temperature device operation. � 2003 Published by Elsevier B.V. PACS: 81.07.Bc; 73.23.Hk; 85.35.Gv
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A memory cell with Single-Electron and metal-oxide-semiconductor transistor integration
Applied Physics Letters, 1999Co-Authors: Zahid A. K. Durrani, A. C. Irvine, Haroon Ahmed, Kazuo NakazatoAbstract:A Single-Electron transistor memory cell with metal-oxide-semiconductor field-effect transistor sensing has been fabricated in silicon-on-insulator material. The Single-Electron transistor, coupled to a memory node, is defined in the upper silicon layer. The memory node forms the gate of a metal-oxide-semiconductor field-effect transistor with its channel in the substrate silicon. At 4.2 K, there are two different states of the memory-node voltage, separated by the Single-Electron transistor Coulomb gap. These states are sensed at high-current output levels by the metal-oxide-semiconductor transistor. The metal-oxide-semiconductor transistor current also shows evidence of gate-dependent conductance oscillations in the coupled Single-Electron transistor.
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Single-Electron devices
Microelectronic Engineering, 1996Co-Authors: Haroon Ahmed, Kazuo NakazatoAbstract:The basic principles of Single-Electron charging effects are explained. The fabrication of island and tunnel junction structures in which Single-Electron devices can be realised is described. Structures based on metals, GaAs/AlGaAs heterointerfaces, @d-doped GaAs, silicon and silicon-on-insulator have been considered and some of the applications of Single Electronics such as the current standard and the Single Electron memory are described in this review.
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Single‐Electron memory
Journal of Applied Physics, 1994Co-Authors: Kazuo Nakazato, Richard J. Blaikie, Haroon AhmedAbstract:A Single‐Electron memory cell, in which one bit of information is represented by the excess or shortfall of a precise number of Electrons, is described. An experimental memory circuit was fabricated using side‐gated constrictions in δ‐doped GaAs, and the basic operation was confirmed from 30 mK up to liquid‐helium temperature of 4.2 K. This memory can store information for longer than several hours. The intrinsic Single‐Electron memory characteristics in a regime where cotunneling is neglected are investigated, and the overall characteristics are explained by a semiclassical model.
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Single-Electron memory
Electronics Letters, 1993Co-Authors: Kazuo Nakazato, Richard J. Blaikie, J. R. A. Cleaver, Haroon AhmedAbstract:A Single-Electron memory cell, in which one bit of information is represented by +n and −n Electron number states, is described. An experimental memory circuit for n ≃100 was fabricated and the basic operation was confirmed at a temperature of 30 mK. This structure can be modified to operate with n = 1.
Alexander N. Korotkov - One of the best experts on this subject based on the ideXlab platform.
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Coulomb Blockade and Digital Single-Electron Devices
2016Co-Authors: Alexander N. KorotkovAbstract:Author(s): Korotkov, Alexander N | Abstract: Tunneling of Single Electrons has been thoroughly studied both theoretically and experimentally during last ten years. By the present time the basic physics is well understood, and creation of useful Single-Electron devices becomes the important issue. Single-Electron tunneling seems to be the most promising candidate to be used in the future integrated digital circuits with the typical size scale of few nanometers and below, i.e. in the molecular Electronics. In the review we first briefly discuss the physics of Single-Electron tunneling and the operation of the Single-Electron transistor. After that, we concentrate on the hypothetical ultradense digital Single-Electron circuits and discuss the different proposed families of them. The last part of the review considers the issues of the discrete energy spectrum and the finite tunnel barrier height which are important for the molecular-size Single-Electron devices.
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Analysis of integrated Single-Electron memory operation
Journal of Applied Physics, 2002Co-Authors: Alexander N. KorotkovAbstract:Various aspects of Single-Electron memory are discussed. In particular, we analyze the Single-Electron charging by Fowler-Nordheim tunneling, propose the idea of background charge compensation, and discuss the defect-tolerant architecture based on nanofuses.
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Single-Electron logic and memory devices
International Journal of Electronics, 1999Co-Authors: Alexander N. KorotkovAbstract:Single-Electronics is believed to be the leading candidate for future digital Electronics which will be able to operate at ~ 10 nm size scale and below. However, the problems of integrated Single-Electronics are quite serious whereby the future prospects are still uncertain. In this paper we discuss the operation principles and required parameters of several proposed families of Single-Electron logic, including the logic based on Single-Electron transistors, wireless Single-Electron logic and Single-Electron parametron. We also briefly discuss the Single-Electron memory which is easier to implement than logic and, hence, is more important from the practical point of view. As an example, we consider the background-charge-insensitive hybrid SET/FET memory.
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Single-Electron-parametron-based logic devices
Journal of Applied Physics, 1998Co-Authors: Alexander N. Korotkov, Konstantin K. LikharevAbstract:We analyze the operation of the wireless Single-Electron logic family based on Single-Electron-parametron cells. Parameter margins, energy dissipation, and the error probability are calculated using the orthodox theory of Single-Electron tunneling. Circuits of this family enable quasi-reversible computation with energy dissipation per bit much lower than the thermal energy, and hence may circumvent one of the main obstacles faced by ultradense three-dimensional integrated digital circuits.
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Single Electron transistor logic
Applied Physics Letters, 1996Co-Authors: R H Chen, Alexander N. Korotkov, K K LikharevAbstract:We present the results of numerical simulations of a functionally complete set of complementary logic circuits based on capacitively coupled Single‐Electron transistors (CSETs). The family includes an inverter/buffer stage, as well as two‐input NOR, NAND, and XOR gates, all using similar tunnel junctions, and the same dc bias voltage and logic levels. Maximum operation temperature, switching speed, power consumption, noise tolerances, error rate, and critical parameter margins of the basic gates have been estimated. When combined with the data from a preliminary geometrical analysis, the results indicate that implementation of the CSET logic family for operation at T∼20 K will require fabrication of structures with ∼2‐nm‐wide islands separated by ∼1‐nm‐wide tunnel gaps.
Yukinori Ono - One of the best experts on this subject based on the ideXlab platform.
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Single-Electron thermal noise.
Nanotechnology, 2014Co-Authors: Katsuhiko Nishiguchi, Yukinori Ono, Akira FujiwaraAbstract:We report the observation of thermal noise in the motion of Single Electrons in an ultimately small dynamic random access memory (DRAM). The nanometer-scale transistors that compose the DRAM resolve the thermal noise in Single-Electron motion. A complete set of fundamental tests conducted on this Single-Electron thermal noise shows that the noise perfectly follows all the aspects predicted by statistical mechanics, which include the occupation probability, the law of equipartition, a detailed balance, and the law of kT/C. In addition, the counting statistics on the directional motion (i.e., the current) of the Single-Electron thermal noise indicate that the individual Electron motion follows the Poisson process, as it does in shot noise.
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Nanotechnology - Single‐Electron Transistor and its Logic Application
Nanotechnology, 2010Co-Authors: Yukinori Ono, Katsuhiko Nishiguchi, Yasuo Takahashi, Hiroshi Inokawa, Akira FujiwaraAbstract:The Single-Electron transistor (SET) is a three-terminal device, the electric characteristics of which are governed by the movement of Single Electrons. The SET's physical size is quite small and its performance, such as ON-OFF current ratio, improves as its size is reduced. The SET is therefore thought to be a promising device for large-scale and low-power integrated circuits. In addition, its current characteristics are unique and much different from those of conventional transistors. This makes the SET one of the best functional devices, and a rich variety of architectures for SET-based logic circuits have been proposed and experimentally tested. This chapter describes SET research from the viewpoint of logic-circuit applications. Keywords: Single-Electron transistor; Single-Electron tunneling; Coulomb blockade; integrated circuit; LSI; logic circuit; quantum dot; power consumption; pass-transistor; multiple-valued logic
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Real-Time Observation of Single-Electron Movement through Silicon Single-Electron Transistor
Japanese Journal of Applied Physics, 2004Co-Authors: Sang Jin Kim, Yukinori Ono, Yasuo Takahashi, Jung Bum ChoiAbstract:We fabricated, for the first time, a device, which enables us to monitor the transport of individual Electrons through a silicon Single-Electron transistor (SET). The device was fabricated on a silicon-on-insulator substrate. In the device, there is a large extra island in one of the SET leads, which exchanges Electrons with the SET. The device also has an electrometer whose current level is sensitive to the potential of the extra island. We observed, at 25 K, that the electrometer current changed in a step like manner as a function of time, which is ascribed to the abrupt change in the extra-island potential due to Single-Electron movement via the SET. This shows that the present structure makes it possible to investigate tunneling dynamics in a silicon SET and to evaluate transfer accuracy of recently demonstrated silicon-based Single-charge-transfer devices.
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Silicon Single-Electron Transistors and Single-Electron CCD
MRS Proceedings, 2001Co-Authors: Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, Hiroshi InokawaAbstract:AbstractWe have developed two types of devices for silicon-Single-Electronics; a Single-Electron transistor (SET) and a Single-Electron charge coupled device (CCD). Both devices were fabricated on SOI (silicon on insulator) wafers. For the SET fabrication, we used a novel method called pattern-dependent oxidation (PADOX), which exploits special phenomena that occur during thermal oxidation of a small silicon structure. The Si structures are converted into small Si SETs by consequence of stress-induced bandgap narrowing and quantum size effects. Since the size of the resultant Si island is about 10 nm, the SETs operate at relatively high temperatures. We have already developed several kinds of application of Si SETs by utilizing the special features of SETs. In addition, we have developed a Single-Electron CCD that enables us to manipulate a Single Electron without tunnel capacitors. The device utilizes small Si-wire MOSFETs connected in series, and an elementary charge can be transferred like in a CCD.
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Single-Electron and quantum SOI devices
Microelectronic Engineering, 2001Co-Authors: Yukinori Ono, Kenji Yamazaki, Masao Nagase, Seiji Horiguchi, Kenji Shiraishi, Yasuo TakahashiAbstract:This paper describes, from the viewpoint of device fabrication, Single-Electron and quantum devices using silicon-on-insulators (SOIs). We point out that control of the oxidation of Si is quite important and could be the key to their fabrication. We also introduce our technique for making Single-Electron transistors (SETs), which uses special phenomena that occur during the oxidation of SOIs, and show that the technique enables us to realize primary Single-Electron circuits as a result of its high controllability and high reproducibility.
Yasuo Takahashi - One of the best experts on this subject based on the ideXlab platform.
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Nanotechnology - Single‐Electron Transistor and its Logic Application
Nanotechnology, 2010Co-Authors: Yukinori Ono, Katsuhiko Nishiguchi, Yasuo Takahashi, Hiroshi Inokawa, Akira FujiwaraAbstract:The Single-Electron transistor (SET) is a three-terminal device, the electric characteristics of which are governed by the movement of Single Electrons. The SET's physical size is quite small and its performance, such as ON-OFF current ratio, improves as its size is reduced. The SET is therefore thought to be a promising device for large-scale and low-power integrated circuits. In addition, its current characteristics are unique and much different from those of conventional transistors. This makes the SET one of the best functional devices, and a rich variety of architectures for SET-based logic circuits have been proposed and experimentally tested. This chapter describes SET research from the viewpoint of logic-circuit applications. Keywords: Single-Electron transistor; Single-Electron tunneling; Coulomb blockade; integrated circuit; LSI; logic circuit; quantum dot; power consumption; pass-transistor; multiple-valued logic
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Real-Time Observation of Single-Electron Movement through Silicon Single-Electron Transistor
Japanese Journal of Applied Physics, 2004Co-Authors: Sang Jin Kim, Yukinori Ono, Yasuo Takahashi, Jung Bum ChoiAbstract:We fabricated, for the first time, a device, which enables us to monitor the transport of individual Electrons through a silicon Single-Electron transistor (SET). The device was fabricated on a silicon-on-insulator substrate. In the device, there is a large extra island in one of the SET leads, which exchanges Electrons with the SET. The device also has an electrometer whose current level is sensitive to the potential of the extra island. We observed, at 25 K, that the electrometer current changed in a step like manner as a function of time, which is ascribed to the abrupt change in the extra-island potential due to Single-Electron movement via the SET. This shows that the present structure makes it possible to investigate tunneling dynamics in a silicon SET and to evaluate transfer accuracy of recently demonstrated silicon-based Single-charge-transfer devices.
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Microscopic Observations of Single-Electron Island in Si Single-Electron Transistors
Japanese Journal of Applied Physics, 2003Co-Authors: Masao Nagase, Akira Fujiwara, Seiji Horiguchi, Yasuo TakahashiAbstract:The three dimensional shapes and sizes of the embedded Si nanostructures in Si Single-Electron transistors (SETs) are observed by using microscopic methods, scanning Electron microscopy (SEM), atomic force microscopy (AFM), and transmission Electron microscopy (TEM). The width of the Si wire in the SET whose conductance oscillations are observed at 25 K is in the range of 7–15 nm measured by SEM. The height of the wire is estimated to be 5–10 nm by AFM. The size of Si wire is small enough to produce the potential barrier caused by the quantum mechanical effect. The effective length of the Single-Electron island is determined from the relationship between the gate capacitance and the length of the Si wire. The effective length is 23 nm shorter than the Si wire length. The distortion in the Si wire in SET is evaluated from the high-resolution image of TEM. The length of the distorted region is almost the same as the effective length of the Single-Electron island. The distortion will produce the potential well in the Si wire. Microscopic observations suggested the existence of potential barriers caused by the quantum mechanical effect and that of the potential well originated from the distortion in the Si wire of SET devices, which agrees with the theoretical model of Si SETs fabricated using pattern-dependent oxidation.
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Silicon Single-Electron Transistors and Single-Electron CCD
MRS Proceedings, 2001Co-Authors: Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, Hiroshi InokawaAbstract:AbstractWe have developed two types of devices for silicon-Single-Electronics; a Single-Electron transistor (SET) and a Single-Electron charge coupled device (CCD). Both devices were fabricated on SOI (silicon on insulator) wafers. For the SET fabrication, we used a novel method called pattern-dependent oxidation (PADOX), which exploits special phenomena that occur during thermal oxidation of a small silicon structure. The Si structures are converted into small Si SETs by consequence of stress-induced bandgap narrowing and quantum size effects. Since the size of the resultant Si island is about 10 nm, the SETs operate at relatively high temperatures. We have already developed several kinds of application of Si SETs by utilizing the special features of SETs. In addition, we have developed a Single-Electron CCD that enables us to manipulate a Single Electron without tunnel capacitors. The device utilizes small Si-wire MOSFETs connected in series, and an elementary charge can be transferred like in a CCD.
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Single-Electron and quantum SOI devices
Microelectronic Engineering, 2001Co-Authors: Yukinori Ono, Kenji Yamazaki, Masao Nagase, Seiji Horiguchi, Kenji Shiraishi, Yasuo TakahashiAbstract:This paper describes, from the viewpoint of device fabrication, Single-Electron and quantum devices using silicon-on-insulators (SOIs). We point out that control of the oxidation of Si is quite important and could be the key to their fabrication. We also introduce our technique for making Single-Electron transistors (SETs), which uses special phenomena that occur during the oxidation of SOIs, and show that the technique enables us to realize primary Single-Electron circuits as a result of its high controllability and high reproducibility.
