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A R M Zaghloul - One of the best experts on this subject based on the ideXlab platform.

  • passive all optical polarization switch Binary Logic gates and digital processor
    Optics Express, 2011
    Co-Authors: Y A Zaghloul, A R M Zaghloul, Ali Adibi
    Abstract:

    We introduce the passive all-optical polarization switch, which modulates light with light. That switch is used to construct all the Binary Logic gates of two or more inputs. We discuss the design concepts and the operation of the AND, OR, NAND, and NOR gates as examples. The rest of the 16 Logic gates are similarly designed. Cascading of such gates is straightforward as we show and discuss. Cascading in itself does not require a power source, but feedback at this stage of development does. The design and operation of an SR Latch is presented as one of the popular basic sequential devices used for memory cells. That completes the essential components of an all-optical polarization digital processor. The speed of such devices is well above 10 GHz for bulk implementations and is much higher for chip-size implementations. In addition, the presented devices do have the four essential characteristics previously thought unique to the microelectronic ones.

  • complete all optical processing polarization based Binary Logic gates and optical processors
    Optics Express, 2006
    Co-Authors: Y A Zaghloul, A R M Zaghloul
    Abstract:

    We present a complete all-optical-processing polarization-based Binary-Logic system, by which any Logic gate or processor can be implemented. Following the new polarization-based Logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either Logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical Logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical Logic architecture for all known and unknown Binary gates, single-branch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all Binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible Logic, and threshold Logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper. * Patent Pending

  • complete all optical processing polarization based Binary Logic gates and optical processors
    Optics Express, 2006
    Co-Authors: Y A Zaghloul, A R M Zaghloul
    Abstract:

    We present a complete all-optical-processing polarization-based Binary-Logic system, by which any Logic gate or processor can be implemented. Following the new polarization-based Logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either Logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical Logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical Logic architecture for all known and unknown Binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all Binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible Logic, and threshold Logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper.

  • unforced polarization based optical implementation of Binary Logic
    Optics Express, 2006
    Co-Authors: Y A Zaghloul, A R M Zaghloul
    Abstract:

    We present a new method to optically represent and implement Binary Logic, and we implement some unforced Logic gates. The Binary Logic zero and one are taken to be an optical beam, or any electromagnetic wave, that is polarized at a selected state and its negation, orthogonal counterpart, or otherwise. In one implementation, a thin-film system is then designed and used so as it can move between 2 positions producing the net desired polarization change of the output. The output consists of a wave that is polarized either in the direction of the original Logic 1 or 0 or any other chosen state and its negation, orthogonal counterpart. The system can be cascaded infinitely due to the fact that the output and input are both of the same format and that the Logic zero and one are not dependant on the intensity of the input or the output light beam. The unforced gates exclusive OR and exclusive NOR along with a simple inverter are demonstrated in this communication. We present three design architectures, where each has two types of gates. In one type of gates the polarization state magnitude can carry information that can be employed for testability or reverse Logic. XOR, XNOR, and inverter gate designs and operation are discussed in detail, and an easy-to-follow step-by-step algorithm is presented. The introduced architectures are easily adapted for simultaneous cascading, multiple input designs, and integrated optical architecture. * Patent Pending.

Y A Zaghloul - One of the best experts on this subject based on the ideXlab platform.

  • passive all optical polarization switch Binary Logic gates and digital processor
    Optics Express, 2011
    Co-Authors: Y A Zaghloul, A R M Zaghloul, Ali Adibi
    Abstract:

    We introduce the passive all-optical polarization switch, which modulates light with light. That switch is used to construct all the Binary Logic gates of two or more inputs. We discuss the design concepts and the operation of the AND, OR, NAND, and NOR gates as examples. The rest of the 16 Logic gates are similarly designed. Cascading of such gates is straightforward as we show and discuss. Cascading in itself does not require a power source, but feedback at this stage of development does. The design and operation of an SR Latch is presented as one of the popular basic sequential devices used for memory cells. That completes the essential components of an all-optical polarization digital processor. The speed of such devices is well above 10 GHz for bulk implementations and is much higher for chip-size implementations. In addition, the presented devices do have the four essential characteristics previously thought unique to the microelectronic ones.

  • complete all optical processing polarization based Binary Logic gates and optical processors
    Optics Express, 2006
    Co-Authors: Y A Zaghloul, A R M Zaghloul
    Abstract:

    We present a complete all-optical-processing polarization-based Binary-Logic system, by which any Logic gate or processor can be implemented. Following the new polarization-based Logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either Logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical Logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical Logic architecture for all known and unknown Binary gates, single-branch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all Binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible Logic, and threshold Logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper. * Patent Pending

  • complete all optical processing polarization based Binary Logic gates and optical processors
    Optics Express, 2006
    Co-Authors: Y A Zaghloul, A R M Zaghloul
    Abstract:

    We present a complete all-optical-processing polarization-based Binary-Logic system, by which any Logic gate or processor can be implemented. Following the new polarization-based Logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either Logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical Logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical Logic architecture for all known and unknown Binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all Binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible Logic, and threshold Logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper.

  • unforced polarization based optical implementation of Binary Logic
    Optics Express, 2006
    Co-Authors: Y A Zaghloul, A R M Zaghloul
    Abstract:

    We present a new method to optically represent and implement Binary Logic, and we implement some unforced Logic gates. The Binary Logic zero and one are taken to be an optical beam, or any electromagnetic wave, that is polarized at a selected state and its negation, orthogonal counterpart, or otherwise. In one implementation, a thin-film system is then designed and used so as it can move between 2 positions producing the net desired polarization change of the output. The output consists of a wave that is polarized either in the direction of the original Logic 1 or 0 or any other chosen state and its negation, orthogonal counterpart. The system can be cascaded infinitely due to the fact that the output and input are both of the same format and that the Logic zero and one are not dependant on the intensity of the input or the output light beam. The unforced gates exclusive OR and exclusive NOR along with a simple inverter are demonstrated in this communication. We present three design architectures, where each has two types of gates. In one type of gates the polarization state magnitude can carry information that can be employed for testability or reverse Logic. XOR, XNOR, and inverter gate designs and operation are discussed in detail, and an easy-to-follow step-by-step algorithm is presented. The introduced architectures are easily adapted for simultaneous cascading, multiple input designs, and integrated optical architecture. * Patent Pending.

Tadahiro Ohmi - One of the best experts on this subject based on the ideXlab platform.

  • neuron mos Binary Logic integrated circuits ii simplifying techniques of circuit configuration and their practical applications
    IEEE Transactions on Electron Devices, 1993
    Co-Authors: Tadashi Shibata, Tadahiro Ohmi
    Abstract:

    For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of Binary-Logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The nu MOS Logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented. >

  • neuron mos Binary Logic integrated circuits i design fundamentals and soft hardware Logic circuit implementation
    IEEE Transactions on Electron Devices, 1993
    Co-Authors: Tadashi Shibata, Tadahiro Ohmi
    Abstract:

    Described are the fundamental design principles for Binary-Logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of bioLogical neurons. To facilitate Logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS Binary-Logic application is the realization of a so-called soft hardware Logic circuit. The circuit can be made to represent any Logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

Tadashi Shibata - One of the best experts on this subject based on the ideXlab platform.

  • neuron mos Binary Logic integrated circuits ii simplifying techniques of circuit configuration and their practical applications
    IEEE Transactions on Electron Devices, 1993
    Co-Authors: Tadashi Shibata, Tadahiro Ohmi
    Abstract:

    For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of Binary-Logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The nu MOS Logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented. >

  • neuron mos Binary Logic integrated circuits i design fundamentals and soft hardware Logic circuit implementation
    IEEE Transactions on Electron Devices, 1993
    Co-Authors: Tadashi Shibata, Tadahiro Ohmi
    Abstract:

    Described are the fundamental design principles for Binary-Logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of bioLogical neurons. To facilitate Logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS Binary-Logic application is the realization of a so-called soft hardware Logic circuit. The circuit can be made to represent any Logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

R D Levine - One of the best experts on this subject based on the ideXlab platform.

  • reconfigurable Logic devices on a single dopant atom operation up to a full adder by using electrical spectroscopy
    ChemPhysChem, 2009
    Co-Authors: Michael Klein, G P Lansbergen, Jan A Mol, S Rogge, R D Levine, Francoise Remacle
    Abstract:

    A silicon field-effect transistor is operated as a Logic circuit by electrically addressing the ground and excited electronic states of an embedded single dopant atom. Experimental results-complemented by analytical and computational calculations-are presented. First, we show how a complete set of Binary Logic gates can be realized on the same hardware. Then, we show that these gates can be operated in parallel on the very same dopant up to the Logic level of a full adder. To use the device not as a switch but as a full Logic circuit, we make essential use of the excited electronic states of the dopant and of the ability to shift their energy by gating. The experimental ability to use two channels to measure the current flowing through the device and the conductance (dI/dV) allows for a robust reading of the output of the Logic operations.

  • transcending Binary Logic by gating three coupled quantum dots
    Nano Letters, 2007
    Co-Authors: Michael Klein, S Rogge, Francoise Remacle, R D Levine
    Abstract:

    Physical considerations supported by numerical solution of the quantum dynamics including electron repulsion show that three weakly coupled quantum dots can robustly execute a complete set of Logic gates for computing using three valued inputs and outputs. Input is coded as gating (up, unchanged, or down) of the terminal dots. A nanosecond time scale switching of the gate voltage requires careful numerical propagation of the dynamics. Readout is the charge (0, 1, or 2 electrons) on the central dot.