The Experts below are selected from a list of 621 Experts worldwide ranked by ideXlab platform
Dmitry Ponomarev - One of the best experts on this subject based on the ideXlab platform.
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Branchscope a new side channel attack on directional Branch predictor
Architectural Support for Programming Languages and Operating Systems, 2018Co-Authors: Dmitry Evtyushkin, Ryan Riley, Nael Cse, Ece Abughazaleh, Dmitry PonomarevAbstract:We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional Branch instruction in a victim program by manipulating the shared directional Branch predictor. The directional component of the Branch predictor stores the prediction on a given Branch (taken or not-taken) and is a different component from the Branch Target Buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional Branch predictor, expanding our understanding of the side channel vulnerability of the Branch prediction unit. Our attack Targets complex hybrid Branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.
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ASPLOS - BranchScope: A New Side-Channel Attack on Directional Branch Predictor
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018Co-Authors: Dmitry Evtyushkin, Ryan Riley, Nael Cse, Ece Abu-ghazaleh, Dmitry PonomarevAbstract:We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional Branch instruction in a victim program by manipulating the shared directional Branch predictor. The directional component of the Branch predictor stores the prediction on a given Branch (taken or not-taken) and is a different component from the Branch Target Buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional Branch predictor, expanding our understanding of the side channel vulnerability of the Branch prediction unit. Our attack Targets complex hybrid Branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.
Dmitry Evtyushkin - One of the best experts on this subject based on the ideXlab platform.
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Branchscope a new side channel attack on directional Branch predictor
Architectural Support for Programming Languages and Operating Systems, 2018Co-Authors: Dmitry Evtyushkin, Ryan Riley, Nael Cse, Ece Abughazaleh, Dmitry PonomarevAbstract:We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional Branch instruction in a victim program by manipulating the shared directional Branch predictor. The directional component of the Branch predictor stores the prediction on a given Branch (taken or not-taken) and is a different component from the Branch Target Buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional Branch predictor, expanding our understanding of the side channel vulnerability of the Branch prediction unit. Our attack Targets complex hybrid Branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.
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ASPLOS - BranchScope: A New Side-Channel Attack on Directional Branch Predictor
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018Co-Authors: Dmitry Evtyushkin, Ryan Riley, Nael Cse, Ece Abu-ghazaleh, Dmitry PonomarevAbstract:We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional Branch instruction in a victim program by manipulating the shared directional Branch predictor. The directional component of the Branch predictor stores the prediction on a given Branch (taken or not-taken) and is a different component from the Branch Target Buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional Branch predictor, expanding our understanding of the side channel vulnerability of the Branch prediction unit. Our attack Targets complex hybrid Branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.
Julian Lewis - One of the best experts on this subject based on the ideXlab platform.
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DAC - The iCOREtm 520 MHz synthesizable CPU core
Proceedings of the 39th conference on Design automation - DAC '02, 2002Co-Authors: Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh H. Soni, Julian LewisAbstract:This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table and a 64 entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm2 in a 6-metal 0.18m CMOS process. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core [1].
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The iCORE/spl trade/ 520 MHz synthesizable CPU core
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002Co-Authors: Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh H. Soni, Julian LewisAbstract:This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table, a 64-entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm/sup 2/ in a 6-metal 0.18 /spl mu/m CMOS process. The design operates up to 520 MHz at 1.8 V, among the highest reported speeds for a synthesized CPU core.
Andreas Moshovos - One of the best experts on this subject based on the ideXlab platform.
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FPL - Low-cost, high-performance Branch predictors for soft processors
2013 23rd International Conference on Field programmable Logic and Applications, 2013Co-Authors: Kaveh Aasaraai, Andreas MoshovosAbstract:This work studies Branch predictor implementations for general purpose, pipelined, single core soft processors. It shows that the existing designs do not map well onto reconfigurable hardware since they were optimized for custom logic implementation. This work then proposes an accurate and fast Branch predictor that uses few resources on FPGAs. The proposed predictor uses: (1) an FPGA-friendly pattern based direction predictor, (2) a return address stack, (3) in-fetch Target address calculation instead of a Branch Target Buffer, and (4) instruction pre-decoding. Experimental measurements using a subset of the SPECCPU2006 workloads show that the presented FPGA-friendly Branch predictor delivers high performance while operating at approximately 259 MHz using only 147 ALUTs and one BRAM on an Altera Stratix IV FPGA.
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phantom btb a virtualized Branch Target Buffer design
Architectural Support for Programming Languages and Operating Systems, 2009Co-Authors: Ioana Burcea, Andreas MoshovosAbstract:Modern processors use Branch Target Buffers (BTBs) to predict the Target address of Branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. Ideally, BTBs would be sufficiently large to capture the entire working set of the application and sufficiently small for fast access and practical on-chip dedicated storage. Depending on the application, these requirements are at odds. This work introduces a BTB design that accommodates large instruction footprints without dedicating expensive onchip resources. In the proposed Phantom-BTB (PBTB) design, a conventional BTB is augmented with a virtual table that collects Branch Target information as the application runs. The virtual table does not have fixed dedicated storage. Instead, it is transparently allocated, on demand, in the on-chip caches, at cache line granularity. The entries in the virtual table are proactively prefetched and installed in the dedicated conventional BTB, thus, increasing its perceived capacity. Experimental results with commercial workloads under full-system simulation demonstrate that PBTB improves IPC performance over a 1K-entry BTB by 6.9% on average and up to 12.7%, with a storage overhead of only 8%. Overall, the virtualized design performs within 1% of a conventional 4K-entry, single-cycle access BTB, while the dedicated storage is 3.6 times smaller.
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ASPLOS - Phantom-BTB: a virtualized Branch Target Buffer design
Proceeding of the 14th international conference on Architectural support for programming languages and operating systems - ASPLOS '09, 2009Co-Authors: Ioana Burcea, Andreas MoshovosAbstract:Modern processors use Branch Target Buffers (BTBs) to predict the Target address of Branches such that they can fetch ahead in the instruction stream increasing concurrency and performance. Ideally, BTBs would be sufficiently large to capture the entire working set of the application and sufficiently small for fast access and practical on-chip dedicated storage. Depending on the application, these requirements are at odds. This work introduces a BTB design that accommodates large instruction footprints without dedicating expensive onchip resources. In the proposed Phantom-BTB (PBTB) design, a conventional BTB is augmented with a virtual table that collects Branch Target information as the application runs. The virtual table does not have fixed dedicated storage. Instead, it is transparently allocated, on demand, in the on-chip caches, at cache line granularity. The entries in the virtual table are proactively prefetched and installed in the dedicated conventional BTB, thus, increasing its perceived capacity. Experimental results with commercial workloads under full-system simulation demonstrate that PBTB improves IPC performance over a 1K-entry BTB by 6.9% on average and up to 12.7%, with a storage overhead of only 8%. Overall, the virtualized design performs within 1% of a conventional 4K-entry, single-cycle access BTB, while the dedicated storage is 3.6 times smaller.
Lizy K. John - One of the best experts on this subject based on the ideXlab platform.
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Advanced Micro Devices
2008Co-Authors: Ravi Bhargava, Lizy K. JohnAbstract:Java programs are increasing in popularity and prevalence on numerous platforms, including high-performance general-purpose processors. The success of Java technology largely depends on the efficiency in executing the portable Java bytecodes. However, the dynamic characteristics of the Java runtime system present unique performance challenges for several aspects of microarchitecture design. In this work, we focus on the effects of indirect Branches on Branch Target address prediction performance. Runtime bytecode translation, just-in-time compilation, frequent calls to the native interface libraries, and dependence on virtual methods increase the frequency of polymorphic indirect Branches. Therefore, accurate Target address prediction for indirect Branches is very important for Java code. This paper characterizes the indirect Branch behavior in Java processing and proposes an adaptive Branch-Target Buffer (BTB) design to enhance the predictability of the Targets. Our characterization shows that a traditional BTB will frequently mispredict a few polymorphic indirect Branches, significantly deteriorating predictor accuracy in Java processing. Therefore, we propose a Rehashable Branch-Target Buffer (R-BTB), which dynamically identifies polymorphic indirect Branches and adapts Branch Target storage to accommodate multiple Targets for a Branch. The R-BTB improves the Target predictability of indirect Branches without sacrificing overall targe
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Adapting Branch-Target Buffer to improve the Target predictability of java code
ACM Transactions on Architecture and Code Optimization, 2005Co-Authors: Ravi Bhargava, Lizy K. JohnAbstract:Java programs are increasing in popularity and prevalence on numerous platforms, including high-performance general-purpose processors. The success of Java technology largely depends on the efficiency in executing the portable Java bytecodes. However, the dynamic characteristics of the Java runtime system present unique performance challenges for several aspects of microarchitecture design. In this work, we focus on the effects of indirect Branches on Branch-Target address prediction performance. Runtime bytecode translation, just-in-time (JIT) compilation, frequent calls to the native interface libraries, and dependence on virtual methods increase the frequency of polymorphic indirect Branches. Therefore, accurate Target address prediction for indirect Branches is very important for Java code.This paper characterizes the indirect Branch behavior in Java processing and proposes an adaptive Branch-Target Buffer (BTB) design to enhance the predictability of the Targets. Our characterization shows that a traditional BTB will frequently mispredict a few polymorphic indirect Branches, significantly deteriorating predictor accuracy in Java processing. Therefore, we propose a rehashable Branch-Target Buffer (R-BTB), which dynamically identifies polymorphic indirect Branches and adapts Branch-Target storage to accommodate multiple Targets for a Branch.The R-BTB improves the Target predictability of indirect Branches without sacrificing overall Target prediction accuracy. Simulations show that the R-BTB eliminates 61p of the indirect Branch mispredictions suffered with a traditional BTB for Java programs running in interpreter mode (46p in JIT mode), which leads to a 57p decrease in overall Target address misprediction rate (29p in JIT mode). With an equivalent number of entries, the R-BTB also outperforms the previously proposed Target cache scheme for a majority of Java programs by adapting to a greater variety of indirect Branch behaviors.
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HiPC - Rehashable BTB: An Adaptive Branch Target Buffer to Improve the Target Predictability of Java Code
High Performance Computing — HiPC 2002, 2002Co-Authors: Ravi Bhargava, Lizy K. JohnAbstract:Java programs are increasing in popularity and prevalence on numerous platforms, including high-performance general-purpose processors. The dynamic characteristics of the Java runtime system present unique performance challenges for several aspects of microarchitecture design. In this work, we focus on the effects of indirect Branches on Branch Target address prediction performance. Runtime bytecode translation, just-in-time compilation, frequent calls to the native interface libraries, and dependence on virtual methods increase the frequency of polymorphic indirect Branches. Therefore, accurate Target address prediction for indirect Branches is very important for Java code. This paper characterizes the indirect Branch behavior in Java processing and proposes an adaptive Branch Target Buffer (BTB) design to enhance the predictability of the Targets. Our characterization shows that a traditional BTB will frequently mispredict polymorphic indirect Branches, significantly deteriorating predictor accuracy in Java processing. Therefore, we propose a Rehashable Branch Target Buffer (R-BTB), which dynamically identifies polymorphic indirect Branches and adapts Branch Target storage to accommodate multiple Targets for a Branch. The R-BTB improves the Target predictability of indirect Branches without sacrificing overall Target prediction accuracy. Simulations show that the R-BTB eliminates 61% of the indirect Branch mispredictions suffered with a traditional BTB for Java programs running in interpreter mode (46% in JIT mode), which leads to a 57% decrease in overall Target address misprediction rate (29% in JIT mode). With an equivalent number of entries, the R-BTB also outperforms the previously proposed Target cache scheme for a majority of Java programs by adapting to a greater variety of indirect Branch behaviors.
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Rehashable BTB: An adaptive Branch Target Buffer to improve the Target predictability of Java code
Lecture Notes in Computer Science, 2002Co-Authors: Ravi Bhargava, Lizy K. JohnAbstract:Java programs are increasing in popularity and prevalence on numerous platforms, including high-performance general-purpose processors. The dynamic characteristics of the Java runtime system present unique performance challenges for several aspects of microarchitecture design. In this work, we focus on the effects of indirect Branches on Branch Target address prediction performance. Runtime bytecode translation, just-in-time compilation, frequent calls to the native interface libraries, and dependence on virtual methods increase the frequency of polymorphic indirect Branches. Therefore, accurate Target address prediction for indirect Branches is very important for Java code. This paper characterizes the indirect Branch behavior in Java processing and proposes an adaptive Branch Target Buffer (BTB) design to enhance the predictability of the Targets. Our characterization shows that a traditional BTB will frequently mispredict polymorphic indirect Branches, significantly deteriorating predictor accuracy in Java processing. Therefore, we propose a Rehashable Branch Target Buffer (R-BTB), which dynamically identifies polymorphic indirect Branches and adapts Branch Target storage to accommodate multiple Targets for a Branch. The R-BTB improves the Target predictability of indirect Branches without sacrificing overall Target prediction accuracy. Simulations show that the R-BTB eliminates 61% of the indirect Branch mispredictions suffered with a traditional BTB for Java programs running in interpreter mode (46% in JIT mode), which leads to a 57% decrease in overall Target address misprediction rate (29% in JIT mode). With an equivalent number of entries, the R-BTB also outperforms the previously proposed Target cache scheme for a majority of Java programs by adapting to a greater variety of indirect Branch behaviors.