The Experts below are selected from a list of 25014 Experts worldwide ranked by ideXlab platform
Marco Platzner - One of the best experts on this subject based on the ideXlab platform.
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FPL - Memory Virtualization for Multithreaded Reconfigurable Hardware
2011 21st International Conference on Field Programmable Logic and Applications, 2011Co-Authors: Andreas Agne, Marco Platzner, Enno LübbersAbstract:With the introduction of multithreaded programming for Reconfigurable Hardware, it is possible to map both sequential software and parallel Hardware to a single CPU/FPGA platform using threads as a unifying development model. At the same time, platform FPGAs are a natural technology for implementing computationally intensive systems in the aerospace, automotive and industrial domains, as they combine high performance and flexibility with lower non-recurring engineering (NRE) costs when compared to low-volume ASIC solutions. The reusability and portability of Hardware components in these safety-critical domains could be significantly improved by using multithreaded programming. However, the unique design considerations for memory virtualization, as required in safety-critical systems, are difficult to transfer directly from software to autonomous Hardware threads. This paper presents a transparent and efficient way of augmenting current multithreaded and partially Reconfigurable Hardware runtime environments with dedicated, Hardware-thread-aware memory address translation units to provide seamless memory translation for Hardware threads. We show an analysis of the overheads, as well as an experimental evaluation of the latencies caused by address translation.
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an edf schedulability test for periodic tasks on Reconfigurable Hardware devices
Languages Compilers and Tools for Embedded Systems, 2006Co-Authors: Klaus Danne, Marco PlatznerAbstract:In this paper, we consider the scheduling of periodic real-time tasks on Reconfigurable Hardware devices. Such devices can execute several tasks in parallel. All executing tasks share the Hardware resource, which makes the scheduling problem differ from single- and multiprocessor scheduling. We adapt the global EDF multiprocessor scheduling approach to the Reconfigurable Hardware execution model and define two preemptive scheduling algorithms, EDF-First-k-Fit and EDF-Next-Fit. For these algorithms, we present a novel linear-time schedulability test and give a proof based on a resource augmentation technique. Then, we propose a task placement and relocation scheme utilizing partial device reconfiguration. This scheme allows us to extend the schedulability test to include reconfiguration time overheads. Experiments with synthetic workloads compare the scheduling test with the actual scheduling performance of EDF-First-k-Fit and EDF-Next-Fit. The main evaluation result is that the reconfiguration overhead is acceptable if the task computation times are one order of magnitude higher than the device reconfiguration time.
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A runtime environment for Reconfigurable Hardware operating systems
Lecture Notes in Computer Science, 2004Co-Authors: Herbert Walder, Marco PlatznerAbstract:We present a runtime environment that partially reconfigures and executes Hardware tasks on Xilinx Virtex. To that end, the FPGA's Reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the Hardware tasks. A bus-based communication infrastructure allows for task communication and I/O. We discuss the design of the runtime system and its prototype implementation on an Reconfigurable board architecture that was specifically tailored to Reconfigurable Hardware operating system research.
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The case for Reconfigurable Hardware in wearable computing
Personal and Ubiquitous Computing, 2003Co-Authors: Christian Plessl, Marco Platzner, Herbert Walder, Rolf Enzler, Jan Beutel, Lothar Thiele, Gerhard TrösterAbstract:Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that Reconfigurable Hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with Reconfigurable modules (WURM). We discuss experiments that show the uses of Reconfigurable Hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.
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ISWC - Reconfigurable Hardware in wearable computing nodes
Proceedings. Sixth International Symposium on Wearable Computers, 1Co-Authors: Christian Plessl, Marco Platzner, Rolf Enzler, Jan Beutel, H. Walder, Lothar ThieleAbstract:Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that Reconfigurable Hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with Reconfigurable modules (WURM). We discuss two experiments that show the uses of Reconfigurable Hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.
Isao Shirakawa - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - A dynamically Reconfigurable Hardware-based cipher chip
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001Co-Authors: Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao ShirakawaAbstract:A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically Reconfigurable Hardware-based cipher, called "Chameleon", in which two 32-cell, 8-context dynamically Reconfigurable Hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 um CMOS3LM technology, using 65.6K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in the mobile computing.
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ISCAS (4) - VLSI architecture of dynamically Reconfigurable Hardware-based cipher
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1Co-Authors: Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao ShirakawaAbstract:This paper describes a 64-bit block, 128-bit key, dynamically Reconfigurable Hardware-based cipher, called Chameleon, in which two 32-cell, 8-context dynamically Reconfigurable Hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by the 0.6 /spl mu/m CMOS 3LM technology, using 65.6 K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in mobile computing.
B. Earl Wells - One of the best experts on this subject based on the ideXlab platform.
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Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment
INFORMS Journal on Computing, 2006Co-Authors: Sin Ming Loo, B. Earl WellsAbstract:This paper describes how static task-scheduling methods using stochastic search techniques can be applied to digital systems that are composed entirely of Reconfigurable Hardware. Such Reconfigurable Hardware is characterized by the property that its low-level logical functionality is not determined at the time of manufacture, but rather that this functionality becomes set only shortly before or during the invocation of the targeted application. The purpose of this paper is to introduce the basic framework for applying static scheduling theory to arbitrarily-structured task systems targeted to be implemented in prefabricated resource-constrained Reconfigurable Hardware. The paper also describes initial solutions to this heterogeneous task-scheduling problem that combine a distributed list-based scheduling technique with three probabilistic search strategies. The techniques introduced produce detailed task scheduling and high-level Hardware configuration information that can serve as inputs to the software and Reconfigurable Hardware design automation tools used in the Hardware/software codesign process.
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Creating an adaptive embedded system by applying multi-agent techniques to Reconfigurable Hardware
Future Generation Computer Systems, 2004Co-Authors: Hamid Reza Naji, B. Earl Wells, Letha H. EtzkornAbstract:This paper describes how the multi-agent paradigm that is so prevalent in today's distributed reactive software systems can be extended to operate in a dynamically adaptable embedded system environment. In this model, both Reconfigurable Hardware and the embedded system software design space can be partitioned into autonomous units of execution that are called agents, where each agent has the capacity to interact with the environment and other agents in an intelligent manner. The incorporation of agents that reside in Reconfigurable Hardware makes it possible to create an intelligent system that exploits the speed advantages associated with Reconfigurable Hardware within the framework of a unified system model that spans the entire Hardware/software continuum. In addition to dynamic adaptability, this approach has the potential to greatly facilitate the flexibility, efficiency, fault tolerance, scalability, and reliability of embedded systems. This paper highlights agent-based Reconfigurable embedded systems, and illustrates how they can he applied to a real-time sensor fusion type application using a conventional Hardware description language.
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Computers and Their Applications - A Genetic Algorithm Approach to Static Task Scheduling in a Reconfigurable Hardware Environment.
2003Co-Authors: Sin Ming Loo, B. Earl Wells, J. D. WinninghamAbstract:This paper presents a basic framework for applying static task scheduling techniques to arbitrarily-structured task systems whose targeted execution environment is comprised of finite amounts of Reconfigurable Hardware. Such Reconfigurable Hardware is characterized by the fact that its structure and logical functionality can be altered any time after the Hardware devices are constructed. Such an environment is assumed to allow for the use of multiple sequential processing elements, task-specific logic and a communication network within the Reconfigurable Hardware. This research focuses upon the application of scheduling theory to a static/deterministic environment where all the task execution times and communication times can be estimated with a great degree of certainty, and the system configuration is determined prior to the execution of the application. The goal of this strategy is to create schedules that have minimal overall execution time under the constraint that the implementation of such schedules does not require more resources of any type than is present within the Reconfigurable Hardware. This scheduling technique conforms in many ways to those applied to the heterogeneous parallel and distributed processing domains but with the addition that the scheduling routines also determines the configuration of the Reconfigurable Hardware as well as creating an ordered list of tasks and communications for each sequential processing element that is employed. This Hardware configuration information includes the type of processors employed, the type of communication that is supported by each data link (buffered or non-buffered), and the interconnection topology needed to support these data links. This paper highlights how a genetic algorithm can be utilized to create schedules for such an environment.
António B. Ferrari - One of the best experts on this subject based on the ideXlab platform.
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a software Reconfigurable Hardware sat solver
IEEE Transactions on Very Large Scale Integration Systems, 2004Co-Authors: Iouliia Skliarova, António B. FerrariAbstract:This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable Hardware. The suggested technique avoids instance-specific Hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resources of the available Reconfigurable Hardware to be solved. The paper presents the results obtained with some of the DIMACS benchmarks and a comparison of our implementation with other available SAT solvers based on Reconfigurable Hardware. The Hardware part of the satisfier was realized on Virtex XCV812E FPGA, which has a large volume of embedded memory blocks that provide direct support for the proposed approach.
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A software/Reconfigurable Hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004Co-Authors: Iouliia Skliarova, António B. FerrariAbstract:This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable Hardware. The suggested technique avoids instance-specific Hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resources of the available Reconfigurable Hardware to be solved. The paper presents the results obtained with some of the DIMACS benchmarks and a comparison of our implementation with other available SAT solvers based on Reconfigurable Hardware. The Hardware part of the satisfier was realized on Virtex XCV812E FPGA, which has a large volume of embedded memory blocks that provide direct support for the proposed approach.
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DATE - A SAT Solver Using Software and Reconfigurable Hardware
2002Co-Authors: Iouliia Skliarova, António B. FerrariAbstract:Summary form only given. In this paper we propose a novel approach for solving the Boolean satisfiability problem by combining software and Reconfigurable Hardware. The suggested technique avoids instance-specific Hardware compilation and, as a result, achieves a higher performance than pure software approaches. Moreover, it permits problems that exceed the resources of the available Reconfigurable Hardware to be solved.
Yukio Mitsuyama - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - A dynamically Reconfigurable Hardware-based cipher chip
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001Co-Authors: Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao ShirakawaAbstract:A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically Reconfigurable Hardware-based cipher, called "Chameleon", in which two 32-cell, 8-context dynamically Reconfigurable Hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 um CMOS3LM technology, using 65.6K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in the mobile computing.
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ISCAS (4) - VLSI architecture of dynamically Reconfigurable Hardware-based cipher
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1Co-Authors: Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao ShirakawaAbstract:This paper describes a 64-bit block, 128-bit key, dynamically Reconfigurable Hardware-based cipher, called Chameleon, in which two 32-cell, 8-context dynamically Reconfigurable Hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by the 0.6 /spl mu/m CMOS 3LM technology, using 65.6 K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in mobile computing.
