The Experts below are selected from a list of 80724 Experts worldwide ranked by ideXlab platform
P J Hurst - One of the best experts on this subject based on the ideXlab platform.
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immediate Calibration of operational amplifier gain error in pipelined adcs using extended correlated double sampling
IEEE Journal of Solid-state Circuits, 2013Co-Authors: O A Hafiz, P J Hurst, Xiaoyue Wang, S H LewisAbstract:This paper introduces extended correlated double sampling (ECDS) as a new gain-Calibration Technique in pipelined analog-to-digital converters (ADCs). The proposed Calibration simultaneously improves the effective dc gain and increases the maximum output swing of the opamps with given overdrive voltages. Furthermore, ECDS is immediate, thus avoiding the long convergence time associated with many background Calibration schemes. This characteristic makes it desirable for applications where the ADC is on only briefly, such as wireless sensor networks (WSNs). An 11-bit 40-MS/s prototype pipelined ADC has been fabricated in 0.25-μm CMOS to demonstrate the proposed Calibration Technique. The active die area is 3.8 mm2 , and the analog power dissipation is 85 mW from a 2.5-V supply. With a 72-kHz input frequency, ECDS improves signal-to-noise-and-distortion ratio from 40.1 to 63.4 dB and spurious-free dynamic range from 41.8 to 75.7 dB.
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a digital background Calibration Technique for time interleaved analog to digital converters
IEEE Journal of Solid-state Circuits, 1998Co-Authors: Daihong Fu, K C Dyer, S H Lewis, P J HurstAbstract:A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background Calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background Calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.
Unku Moon - One of the best experts on this subject based on the ideXlab platform.
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an on chip Calibration Technique for reducing supply voltage sensitivity in ring oscillators
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A Technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip Calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip Calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the Calibration circuitry is 0.064 mm2
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an on chip Calibration Technique for reducing supply voltage sensitivity in ring oscillators
Symposium on VLSI Circuits, 2006Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A Technique for reducing ring oscillator supply voltage sensitivity using on-chip Calibration is described. A 1V 0.13mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 500MHz-2GHz. The measured rms jitter of the proposed PLL with on-chip Calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 1MHz VCO supply noise, while a conventional VCO measures 19.4ps rms jitter. The total power consumption of the PLL is 9.4mW, and the core die area of the PLL with Calibration circuitry is 0.064mm2
Jiehtsorng Wu - One of the best experts on this subject based on the ideXlab platform.
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a background timing skew Calibration Technique for time interleaved analog to digital converters
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2006Co-Authors: Chungyi Wang, Jiehtsorng WuAbstract:This paper presents a background timing-skew Calibration Technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the A/D channels caused by the mismatches among the clock routes. The Calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example.
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a background comparator Calibration Technique for flash analog to digital converters
IEEE Transactions on Circuits and Systems, 2005Co-Authors: Chuncheng Huang, Jiehtsorng WuAbstract:This paper presents a background Calibration Technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All Calibration procedures are performed in the digital domain. The Calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in Calibration settling time and an increase in /spl sigma/(V/sub OS/). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.
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a background comparator Calibration Technique for flash analog to digital converters
International Symposium on VLSI Design Automation and Test, 2005Co-Authors: Chuncheng Huang, Jiehtsorng WuAbstract:In modern integrated circuit systems, the flash ADC, which simultaneously compares input signal, is most suitable for high speed analog-to-digital conversion since it doesn't require linear amplification. Due to the random input-referred offset voltage of the comparators, the linearity of the ADC transfer function is degraded. This offset is caused by device mismatches. And to overcome this inherent device's constraint, several Techniques have been proposed. This paper describes a background Calibration Technique that can perform offset trimming in comparators without interrupting the normal operation of the ADC. Since most of the required circuit overhead for the proposed scheme is in the digital domain and little modification is done to the analog critical signal path, the proposed scheme won't degrade the speed of the circuit's comparison function.
S H Lewis - One of the best experts on this subject based on the ideXlab platform.
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immediate Calibration of operational amplifier gain error in pipelined adcs using extended correlated double sampling
IEEE Journal of Solid-state Circuits, 2013Co-Authors: O A Hafiz, P J Hurst, Xiaoyue Wang, S H LewisAbstract:This paper introduces extended correlated double sampling (ECDS) as a new gain-Calibration Technique in pipelined analog-to-digital converters (ADCs). The proposed Calibration simultaneously improves the effective dc gain and increases the maximum output swing of the opamps with given overdrive voltages. Furthermore, ECDS is immediate, thus avoiding the long convergence time associated with many background Calibration schemes. This characteristic makes it desirable for applications where the ADC is on only briefly, such as wireless sensor networks (WSNs). An 11-bit 40-MS/s prototype pipelined ADC has been fabricated in 0.25-μm CMOS to demonstrate the proposed Calibration Technique. The active die area is 3.8 mm2 , and the analog power dissipation is 85 mW from a 2.5-V supply. With a 72-kHz input frequency, ECDS improves signal-to-noise-and-distortion ratio from 40.1 to 63.4 dB and spurious-free dynamic range from 41.8 to 75.7 dB.
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a digital background Calibration Technique for time interleaved analog to digital converters
IEEE Journal of Solid-state Circuits, 1998Co-Authors: Daihong Fu, K C Dyer, S H Lewis, P J HurstAbstract:A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background Calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background Calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.
Kartikeya Mayaram - One of the best experts on this subject based on the ideXlab platform.
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an on chip Calibration Technique for reducing supply voltage sensitivity in ring oscillators
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A Technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip Calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip Calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the Calibration circuitry is 0.064 mm2
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an on chip Calibration Technique for reducing supply voltage sensitivity in ring oscillators
Symposium on VLSI Circuits, 2006Co-Authors: Kartikeya Mayaram, Unku MoonAbstract:A Technique for reducing ring oscillator supply voltage sensitivity using on-chip Calibration is described. A 1V 0.13mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 500MHz-2GHz. The measured rms jitter of the proposed PLL with on-chip Calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 1MHz VCO supply noise, while a conventional VCO measures 19.4ps rms jitter. The total power consumption of the PLL is 9.4mW, and the core die area of the PLL with Calibration circuitry is 0.064mm2
