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Yi-shao Lai - One of the best experts on this subject based on the ideXlab platform.

  • Reliability and Characteristics for Wafer Level Chip Scale Packages under Current Stressing
    2014
    Co-Authors: Po-ying Chen, Yi-shao Lai, Heng-yu Kung, Ming Hsiung Tsai, Wen-kuan Yeh
    Abstract:

    This work presents a novel approach and method for examining the characteristics of wafer-level Chip-Scale Packages (WLCSPs) for electro migration (EM) tests. The die in the WLCSP was directly attached to the substrate via a soldered interconnect. The die shrinks area available for power and the solder bump also shrinks volume and increase quantity of electron for interconnect efficiency. The bump current density now approaches 106 A/cm2, at which point the electromigration (EM) becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness and others. New interconnection geometry has been used utilized extensively with moderate success in overcoming larger mismatches in components displacements during current and temperature excursions. Both the environments and testing qualifications for these Packages are becoming increasingly more and more demanding. Failure mechanisms once considered eliminated, or at least reduced to a manageable extent in new package technology designs, are again challenging process integrity and reliability. Especially for WLCSPs, which were first designed to eliminate any need for encapsulation to be compatible with the smart-mount technology (SMT) process, and to have good handing properties fac

  • electromigration reliability of redistribution lines in wafer level Chip Scale Packages
    Electronic Components and Technology Conference, 2011
    Co-Authors: Yi-shao Lai, Chinli Kao, Yingta Chiu, Bernd K Appelt
    Abstract:

    Wafer-level Chip-Scale Packages (WLCSPs) have become subject to the same drive for miniaturization as all electronic Packages. The I/O count is increasing and ball pitch is shrinking at the expense of trace pitch and in turn, current densities are increasing. This leads to current crowding and Joule heating in the vicinity of solder joints and under bump metallurgy (UBM) structures where resistance values change significantly. These phenomena are responsible for structural damage of redistribution line (RDL)/UBM and UBM/solder interconnects due to ionic diffusion or electromigration. In this work, sputtered Al and electroplated Cu RDLs are examined and quantified by three-dimensional electrothermal coupling analysis. Results provide a guideline for estimating maximum allowable currents and electromigration lifetime.

  • structural design optimization for board level drop reliability of wafer level Chip Scale Packages
    Microelectronics Reliability, 2008
    Co-Authors: Tsungyueh Tsai, Yi-shao Lai, Changlin Yeh, Rongsheng Chen
    Abstract:

    Abstract In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level Chip-Scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L 9 (3 4 ) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.

  • characterizations of ball impact responses of wafer level Chip Scale Packages
    Journal of Alloys and Compounds, 2008
    Co-Authors: Yi-shao Lai, Changlin Yeh, Hsiao-chuan Chang, Chinli Kao
    Abstract:

    Abstract We present in this paper ball impact test results conducted on package-level 95.5Sn–4Ag–0.5Cu solder joints of a wafer-level Chip-Scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after the ball impact test, respectively. An explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles are presented. The comparison indicates that when material properties and strengths are apppropriately and reasonably selected, the finite element analysis is capable of capturing relevant ball impact test (BIT)-induced transient structural responses of the solder joint prior to the initiation of fracturing.

  • effects of different drop test conditions on board level reliability of Chip Scale Packages
    Microelectronics Reliability, 2008
    Co-Authors: Yi-shao Lai, Pochuan Yang, Changlin Yeh
    Abstract:

    Abstract In this study, reliability performances of board-level Chip-Scale Packages subjected to four JEDEC drop test conditions: A (500 G; 1.0 ms), B (1500 G; 0.5 ms), F (900 G; 0.7 ms), and H (2900 G; 0.3 ms) were evaluated experimentally and numerically. For each of the test conditions, over 80% of the failed solder joints fractured on the package side. Among the four test conditions, condition A led to the best drop resistance while condition H the worst. Though drop resistances resulted from conditions B and F were close to each other, the former contained a greater portion of failure identified as test board pad peeling. Numerical solutions of interfacial stresses, obtained by the transient finite element analysis, provided a supporting basis for the crack propagation observed from the experiments, for which the crack initiated from the inner corner of the solder joint on the package side and propagated outwards. The strain rates were found to be within 102 s−1 for the four drop test conditions. Using computed maximum interfacial normal and shear stresses, a fatigue reliability model that predicts the drop counts for different drop test conditions was established.

Xuejun Fan - One of the best experts on this subject based on the ideXlab platform.

  • effects of voids on mechanical and thermal properties of the die attach solder layer used in high power led Chip Scale Packages
    IEEE Transactions on Components Packaging and Manufacturing Technology, 2018
    Co-Authors: Chengshuo Jiang, Jiajie Fan, Xuejun Fan, Cheng Qian, Hao Zhang, Weiling Guo, G Q Zhang
    Abstract:

    High-power light-emitting diode (LED) Chip-Scale Packages (CSPs) prepared by the flip-Chip technology have become one of the most promising light sources. The die attach solder layer always plays an important role in heat dissipation, mechanical support, and electronic conductivity. Among different types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy shows its great competitiveness on solderability and mechanical properties for the interconnection of high-power LED CSPs. However, reliability problems caused by voids in the SAC305 solder limit its wide application in the high-power LED Chip-Scale packaging process. Existence of the voids has been considered as one of the major issues causing Chip-on-substrate level reliability problems in microelectronic and optoelectronic devices. In this paper, mechanical and thermal properties of SAC305 solder layers with arbitrary voids used in high-power LED CSPs are studied with both finite-element simulations and experiments. The results show that void size and void position within the solder layer are the two most critical issues on the shear strength of interconnection and the Chip-on-substrate level thermal distribution in high-power LED CSPs.

  • Fatigue Damage Assessment of LED Chip Scale Packages with Finite Element Simulation
    2018 19th International Conference on Electronic Packaging Technology (ICEPT), 2018
    Co-Authors: Jiajie Fan, Michael Pecht, Wei Chen, Xuejun Fan, Guoqi Zhang
    Abstract:

    As one of solid state lighting sources, wafer-level Chip Scale Light Emitting Diode (LED) Packages has gained much attention, because of its compact size, high power and high optical performance. For this package to be effective, the solder layer plays the critical role in heat dissipation, mechanical support and electrical conductivity. Among all types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy is considered as one of best Chip-attachment candidates due to its acceptable cost, good solderability, and favorable shear strength. However, such solder connections are prone to fatigue over time due to thermal or power cycling. This paper models the wafer level Chip Scale LEDs soldered on both aluminum oxide and aluminum substrates with SAC305 solder alloy. Thermal cycling conditions are simulated to assess the fatigue damage of the solder interconnection. Von Mises stress and plastic work density are utilized to represent the fatigue damage per cycle by using finite element analysis (FEA) method. Important design considerations include the effects of LED Chip substrate, thickness of the solder interconnections, void ratio in the solder connections and PCB substrate. The result is a set of fatigue damage accumulation metrics.

  • photometric and colorimetric assessment of led Chip Scale Packages by using a step stress accelerated degradation test ssadt method
    Materials, 2017
    Co-Authors: Cheng Qian, Jiajie Fan, Xuejun Fan, Jiayi Fang, Yi Ren, G Q Zhang
    Abstract:

    By solving the problem of very long test time on reliability qualification for Light-emitting Diode (LED) products, the accelerated degradation test with a thermal overstress at a proper range is regarded as a promising and effective approach. For a comprehensive survey of the application of step-stress accelerated degradation test (SSADT) in LEDs, the thermal, photometric, and colorimetric properties of two types of LED Chip Scale Packages (CSPs), i.e., 4000 °K and 5000 °K samples each of which was driven by two different levels of currents (i.e., 120 mA and 350 mA, respectively), were investigated under an increasing temperature from 55 °C to 150 °C and a systemic study of driving current effect on the SSADT results were also reported in this paper. During SSADT, junction temperatures of the test samples have a positive relationship with their driving currents. However, the temperature-voltage curve, which represents the thermal resistance property of the test samples, does not show significant variance as long as the driving current is no more than the sample's rated current. But when the test sample is tested under an overdrive current, its temperature-voltage curve is observed as obviously shifted to the left when compared to that before SSADT. Similar overdrive current affected the degradation scenario is also found in the attenuation of Spectral Power Distributions (SPDs) of the test samples. As used in the reliability qualification, SSADT provides explicit scenes on color shift and correlated color temperature (CCT) depreciation of the test samples, but not on lumen maintenance depreciation. It is also proved that the varying rates of the color shift and CCT depreciation failures can be effectively accelerated with an increase of the driving current, for instance, from 120 mA to 350 mA. For these reasons, SSADT is considered as a suitable accelerated test method for qualifying these two failure modes of LED CSPs.

  • thermal luminescence characterization and degradation mechanism analysis on phosphor converted white led Chip Scale Packages
    Microelectronics Reliability, 2017
    Co-Authors: Jiajie Fan, Xuejun Fan, Cheng Qian, G Q Zhang
    Abstract:

    Abstract According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED Chips by impressing a thin phosphor film on LED blue Chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate Chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.

  • modeling of moisture over saturation and vapor pressure in die attach film for stacked die Chip Scale Packages
    Journal of Materials Science: Materials in Electronics, 2016
    Co-Authors: Liangbiao Chen, Jeremy Adams, Hsingwei Chu, Xuejun Fan
    Abstract:

    Die-attach film failure during soldering reflow is of particular concern for reliability of 3D ultra-thin stacked-die Chip Scale Packages (CSPs), as extremely high vapor pressure can be generated from vaporized moisture to cause severe damages. Under rapid heating, pressure-driven moisture vapor flow could become as significant as concentration-driven diffusion, and should be included in moisture transport models. In this study, a convection–diffusion (CD) model is presented for analyzing vapor pressure and moisture behavior of soft die-attach films for 3D CSPs, with both vapor flow and the effect of temperature on saturated moisture content considered. By using a 1D model according to experimental observations, the over-saturation phenomenon in the thin film and vapor pressure evolution are investigated. It is found that the reflow profiles and substrate thickness could have great impact on the magnitude of vapor pressure, which agrees well with the experimental results. Sensitivity analyses show that a high vapor permeability and a large porosity could lead to low vapor pressure. Being a vapor pressure-based model, the CD model is suitable to study multiple-material systems without discontinuity issue at the material boundary. It is concluded that the CD model could serve as an effective method for predicting vapor pressure and moisture behaviors during soldering reflow for 3D stacked-die CSPs.

Tong Hong Wang - One of the best experts on this subject based on the ideXlab platform.

  • reliability evaluations for board level Chip Scale Packages under coupled power and thermal cycling test conditions
    Microelectronics Reliability, 2008
    Co-Authors: Tong Hong Wang, Yi-shao Lai, Yucheng Lin
    Abstract:

    Abstract To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic Packages, a coupled power and thermal cycling test has been proposed. In this study, the sequential thermal–mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array Chip-Scale Packages under coupled power and thermal cycling test conditions. Effects of different power cycling durations are studied. A pure thermal cycling condition is also examined and compared. Numerical results indicate that, for the coupled power and thermal cycling test, a shorter power cycling duration in general leads to a shorter fatigue life. However, the temperature compensation effect elongates the fatigue life under certain power cycling durations.

  • Cyclic bending reliability of wafer-level Chip-Scale Packages.
    Microelectronics Reliability, 2007
    Co-Authors: Yi-shao Lai, Tong Hong Wang, Han-hui Tsai, Ming-hwa R. Jen
    Abstract:

    In this paper, both experimental and numerical studies are conducted to investigate board-level reliability of wafer-level Chip-Scale Packages under four-point cyclic bending conditions that combine different deflection amplitudes and excitation frequencies. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints are observed. In the numerical modeling, inertia forces along with rate-dependent material properties of the solder joints are considered in order to capture frequency-dependent characteristics of this particular test methodology. Through the dynamic finite element analysis, plastic strain energy densities accumulated per bending cycle within the critical solder joint are calculated and together with the experimental results, parameters for the Morrow fatigue model are calibrated.

  • optimal design towards enhancement of board level thermomechanical reliability of wafer level Chip Scale Packages
    Microelectronics Reliability, 2007
    Co-Authors: Yi-shao Lai, Tong Hong Wang
    Abstract:

    In this paper we study board-level thermomechanical reliability of a wafer-level Chip-Scale package subjected to an accelerated thermal cycling test condition. Different control factors are considered for a robust design towards enhancement of the thermal fatigue resistance of solder joints. These factors include diameter, pitch, and standoff of the solder joints, size of the solder connection opening on the die side, thickness of the pad on the test board, thickness of the test board, and dimension of the die. The Taguchi method along with the technique of analysis of variance are applied in the robust design process. Importance of these factors on the thermomechanical reliability of the package is ranked and the resulting robust design is further verified.

  • board level power cycling and thermal cycling fatigue reliability of Chip Scale Packages
    Journal of microelectronics and electronic packaging, 2005
    Co-Authors: Tong Hong Wang, Yi-shao Lai, Changchi Lee
    Abstract:

    In this paper, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, was carried out to investigate board-level fatigue reliability of a thin profile and fine pitch ball grid array (TFBGA) Chip-Scale package under accelerated power cycling test conditions. Experiments for steady-state and transient thermal dissipations were conducted to verify the thermal analysis. Comparing between numerical results for power cycling and thermal cycling, it is noticed that for the tests with similar low and high temperature extremes, power cycling results in a much longer fatigue life than thermal cycling, which indicates that thermal cycling is a more conservative criterion than power cycling is in evaluating the fatigue resistance of the electronic Packages.

  • thermal mechanical coupling analysis for coupled power and thermal cycling reliability of Chip Scale Packages
    International Conference on Thermal Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005
    Co-Authors: Yi-shao Lai, Tong Hong Wang, Changchi Lee
    Abstract:

    The sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermo-mechanical deformations, is carried out in this paper to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array Chip-Scale Packages under coupled power and thermal cycling test conditions. Pure thermal cycling and pure power cycling test conditions are also examined and compared.

G Q Zhang - One of the best experts on this subject based on the ideXlab platform.

  • effects of voids on mechanical and thermal properties of the die attach solder layer used in high power led Chip Scale Packages
    IEEE Transactions on Components Packaging and Manufacturing Technology, 2018
    Co-Authors: Chengshuo Jiang, Jiajie Fan, Xuejun Fan, Cheng Qian, Hao Zhang, Weiling Guo, G Q Zhang
    Abstract:

    High-power light-emitting diode (LED) Chip-Scale Packages (CSPs) prepared by the flip-Chip technology have become one of the most promising light sources. The die attach solder layer always plays an important role in heat dissipation, mechanical support, and electronic conductivity. Among different types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy shows its great competitiveness on solderability and mechanical properties for the interconnection of high-power LED CSPs. However, reliability problems caused by voids in the SAC305 solder limit its wide application in the high-power LED Chip-Scale packaging process. Existence of the voids has been considered as one of the major issues causing Chip-on-substrate level reliability problems in microelectronic and optoelectronic devices. In this paper, mechanical and thermal properties of SAC305 solder layers with arbitrary voids used in high-power LED CSPs are studied with both finite-element simulations and experiments. The results show that void size and void position within the solder layer are the two most critical issues on the shear strength of interconnection and the Chip-on-substrate level thermal distribution in high-power LED CSPs.

  • photometric and colorimetric assessment of led Chip Scale Packages by using a step stress accelerated degradation test ssadt method
    Materials, 2017
    Co-Authors: Cheng Qian, Jiajie Fan, Xuejun Fan, Jiayi Fang, Yi Ren, G Q Zhang
    Abstract:

    By solving the problem of very long test time on reliability qualification for Light-emitting Diode (LED) products, the accelerated degradation test with a thermal overstress at a proper range is regarded as a promising and effective approach. For a comprehensive survey of the application of step-stress accelerated degradation test (SSADT) in LEDs, the thermal, photometric, and colorimetric properties of two types of LED Chip Scale Packages (CSPs), i.e., 4000 °K and 5000 °K samples each of which was driven by two different levels of currents (i.e., 120 mA and 350 mA, respectively), were investigated under an increasing temperature from 55 °C to 150 °C and a systemic study of driving current effect on the SSADT results were also reported in this paper. During SSADT, junction temperatures of the test samples have a positive relationship with their driving currents. However, the temperature-voltage curve, which represents the thermal resistance property of the test samples, does not show significant variance as long as the driving current is no more than the sample's rated current. But when the test sample is tested under an overdrive current, its temperature-voltage curve is observed as obviously shifted to the left when compared to that before SSADT. Similar overdrive current affected the degradation scenario is also found in the attenuation of Spectral Power Distributions (SPDs) of the test samples. As used in the reliability qualification, SSADT provides explicit scenes on color shift and correlated color temperature (CCT) depreciation of the test samples, but not on lumen maintenance depreciation. It is also proved that the varying rates of the color shift and CCT depreciation failures can be effectively accelerated with an increase of the driving current, for instance, from 120 mA to 350 mA. For these reasons, SSADT is considered as a suitable accelerated test method for qualifying these two failure modes of LED CSPs.

  • thermal luminescence characterization and degradation mechanism analysis on phosphor converted white led Chip Scale Packages
    Microelectronics Reliability, 2017
    Co-Authors: Jiajie Fan, Xuejun Fan, Cheng Qian, G Q Zhang
    Abstract:

    Abstract According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED Chips by impressing a thin phosphor film on LED blue Chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate Chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.

Yang Jian-sheng - One of the best experts on this subject based on the ideXlab platform.

  • Rework Techniques Process Evaluation for Chip Scale Packages
    Electronics & Packaging, 2008
    Co-Authors: Yang Jian-sheng
    Abstract:

    The Chip Scale package (CSP) and ball grid array (BGA) have allowed significant reductions in component size compared to conventional surface mount devices (SMD) such as quad flat packs (QFP). However, the position of the solder joints formed (underneath the Chip) after reflow means that visual inspection is impossible. For the defective Chip, the only realistic method of rework is to remove and replace it. Component removal can be easily achieved, however replacement may be more complex.Two PCB pad- cleaning methods have been compared and conclusion drawn from the resultant pad finish. In the first technique, a hot nitrogen de-soldering gun was used to reflow any residual solder on the pad, which was then removed by a vacuum once liquefied. The second technique involved using braided solder wick and a soldering iron with a blade tip to remove residual solder from the PCB pad.Four deposition techniques have been assessed; these includes mini-stencil, dip transfer, on-and off-contact stamping. Mini-stencil is the traditional method used in the electronics manufacturing industry for the deposition of solder paste onto reworked component sites.

  • Wafer-Level Chip Scale Packaging Benefits Integrated Passive Devices
    Equipment for Electronic Products Manufacturing, 2007
    Co-Authors: Yang Jian-sheng
    Abstract:

    Chip Scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term Chip Scale package (CSP) has become synonymous with "fine pitch BGA" as the distinction between a ball grid array (BGA) and some Chip Scale Packages become nearly indistinguishable. The cost of Chip Scale Packages also continues to draw attention as one of the barriers to wide Scale industry adoption. Sometimes lost in the Chip Scale debate is the discussion about wafer level Chip Scale Packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, an approach to wafer level Chip Scale packaging that is an extension of integrated passive device processing is described, which results in low cost.