The Experts below are selected from a list of 27234 Experts worldwide ranked by ideXlab platform
Hao Zheng - One of the best experts on this subject based on the ideXlab platform.
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high sensitivity and wide dynamic range analog front end Circuits for pulsed tof 4 d imaging ladar receiver
IEEE Sensors Journal, 2018Co-Authors: Hao Zheng, Maliang Liu, Zhangming ZhuAbstract:Analog front-end (AFE) Circuits, which mainly consist of a transimpedance amplifier (TIA) with wide dynamic range and a timing discriminator with double threshold voltage, were designed and implemented for a pulsed time-of-fight 4-D imaging LADAR receiver. The preamplifier of the proposed TIA adopts a shunt-feedback topology to amplify weak echo signal, and a current-mirror topology to amplify strong one, respectively. The proposed AFE can capture directly the pulsed echo amplitude with wide dynamic range through programmable gain control switches. The proposed AFE Circuits, which achieve a high gain of 106 dB $\Omega $ , a linear dynamic range of 80 dB, an averaged input-referred noise density of 0.89 pA/Hz0.5 and a minimum detectable signal of $0.36~\mu \text{A}$ at SNR = 5, and a sensitivity of 8 nW with APD of 45 A/W, were designed with 3.3 V devices and fabricated in a 0.18- $\mu \text{m}$ standard CMOS process. The total area of AFE, which includes the Circuit Core, bandgap and bias Circuits, and I/O PAD, is approximately equal to $1.20\times 1.13$ mm2.
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high sensitivity and wide dynamic range analog front end Circuits for pulsed tof 4 d imaging ladar receiver
IEEE Sensors Journal, 2018Co-Authors: Hao ZhengAbstract:Analog front-end (AFE) Circuits, which mainly consist of a transimpedance amplifier (TIA) with wide dynamic range and a timing discriminator with double threshold voltage, were designed and implemented for a pulsed time-of-fight 4-D imaging LADAR receiver. The preamplifier of the proposed TIA adopts a shunt-feedback topology to amplify weak echo signal, and a current-mirror topology to amplify strong one, respectively. The proposed AFE can capture directly the pulsed echo amplitude with wide dynamic range through programmable gain control switches. The proposed AFE Circuits, which achieve a high gain of 106 dB $\Omega $ , a linear dynamic range of 80 dB, an averaged input-referred noise density of 0.89 pA/Hz0.5 and a minimum detectable signal of $0.36~\mu \text{A}$ at SNR = 5, and a sensitivity of 8 nW with APD of 45 A/W, were designed with 3.3 V devices and fabricated in a 0.18- $\mu \text{m}$ standard CMOS process. The total area of AFE, which includes the Circuit Core, bandgap and bias Circuits, and I/O PAD, is approximately equal to $1.20\times 1.13$ mm2.
Zhangming Zhu - One of the best experts on this subject based on the ideXlab platform.
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high sensitivity and wide dynamic range analog front end Circuits for pulsed tof 4 d imaging ladar receiver
IEEE Sensors Journal, 2018Co-Authors: Hao Zheng, Maliang Liu, Zhangming ZhuAbstract:Analog front-end (AFE) Circuits, which mainly consist of a transimpedance amplifier (TIA) with wide dynamic range and a timing discriminator with double threshold voltage, were designed and implemented for a pulsed time-of-fight 4-D imaging LADAR receiver. The preamplifier of the proposed TIA adopts a shunt-feedback topology to amplify weak echo signal, and a current-mirror topology to amplify strong one, respectively. The proposed AFE can capture directly the pulsed echo amplitude with wide dynamic range through programmable gain control switches. The proposed AFE Circuits, which achieve a high gain of 106 dB $\Omega $ , a linear dynamic range of 80 dB, an averaged input-referred noise density of 0.89 pA/Hz0.5 and a minimum detectable signal of $0.36~\mu \text{A}$ at SNR = 5, and a sensitivity of 8 nW with APD of 45 A/W, were designed with 3.3 V devices and fabricated in a 0.18- $\mu \text{m}$ standard CMOS process. The total area of AFE, which includes the Circuit Core, bandgap and bias Circuits, and I/O PAD, is approximately equal to $1.20\times 1.13$ mm2.
Maliang Liu - One of the best experts on this subject based on the ideXlab platform.
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high sensitivity and wide dynamic range analog front end Circuits for pulsed tof 4 d imaging ladar receiver
IEEE Sensors Journal, 2018Co-Authors: Hao Zheng, Maliang Liu, Zhangming ZhuAbstract:Analog front-end (AFE) Circuits, which mainly consist of a transimpedance amplifier (TIA) with wide dynamic range and a timing discriminator with double threshold voltage, were designed and implemented for a pulsed time-of-fight 4-D imaging LADAR receiver. The preamplifier of the proposed TIA adopts a shunt-feedback topology to amplify weak echo signal, and a current-mirror topology to amplify strong one, respectively. The proposed AFE can capture directly the pulsed echo amplitude with wide dynamic range through programmable gain control switches. The proposed AFE Circuits, which achieve a high gain of 106 dB $\Omega $ , a linear dynamic range of 80 dB, an averaged input-referred noise density of 0.89 pA/Hz0.5 and a minimum detectable signal of $0.36~\mu \text{A}$ at SNR = 5, and a sensitivity of 8 nW with APD of 45 A/W, were designed with 3.3 V devices and fabricated in a 0.18- $\mu \text{m}$ standard CMOS process. The total area of AFE, which includes the Circuit Core, bandgap and bias Circuits, and I/O PAD, is approximately equal to $1.20\times 1.13$ mm2.
Hsinming Wu - One of the best experts on this subject based on the ideXlab platform.
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a 2 5 gb s dll based burst mode clock and data recovery Circuit with 4 times oversampling
IEEE Transactions on Very Large Scale Integration Systems, 2015Co-Authors: Chingyuan Yang, Hsinming WuAbstract:In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) Circuit using a $4\times$ oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed Circuit can recover the burst-mode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18- $\mu{\rm m}$ CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of $2^{31}{-}1$ pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peak-to-peak jitter of 32.0 ps, and the measured bit error rate is less than $10^{-10}$ . The area of the whole chip is 1.4 $\,\times\,$ 1.4 ${\rm mm}^{2}$ , where the BMCDR Circuit Core occupies 0.81 $\,\times\,$ 0.325 ${\rm mm}^{2}$ . The total power consumption is 130 mW from a 1.8 V supply voltage.
Chingyuan Yang - One of the best experts on this subject based on the ideXlab platform.
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a 2 5 gb s dll based burst mode clock and data recovery Circuit with 4 times oversampling
IEEE Transactions on Very Large Scale Integration Systems, 2015Co-Authors: Chingyuan Yang, Hsinming WuAbstract:In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) Circuit using a $4\times$ oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed Circuit can recover the burst-mode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18- $\mu{\rm m}$ CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of $2^{31}{-}1$ pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peak-to-peak jitter of 32.0 ps, and the measured bit error rate is less than $10^{-10}$ . The area of the whole chip is 1.4 $\,\times\,$ 1.4 ${\rm mm}^{2}$ , where the BMCDR Circuit Core occupies 0.81 $\,\times\,$ 0.325 ${\rm mm}^{2}$ . The total power consumption is 130 mW from a 1.8 V supply voltage.