The Experts below are selected from a list of 18216 Experts worldwide ranked by ideXlab platform
Ram Krishnamurthy - One of the best experts on this subject based on the ideXlab platform.
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a 4 fj b Delay hardened physically unclonable function circuit with selective bit destabilization in 14 nm trigate cmos
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Sudhir K Satpathy, Sanu Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Vikram B Suresh, Steven K Hsu, Gregory K Chen, Ram KrishnamurthyAbstract:This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential Clock Delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid Clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.
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a 4fj bit Delay hardened physically unclonable function circuit with selective bit destabilization in 14nm tri gate cmos
Symposium on VLSI Circuits, 2016Co-Authors: Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Greg Chen, Ram Krishnamurthy, Vivek DeAbstract:A 1024-bit Delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential Clock Delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.
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2 4 gbps 7 mw all digital pvt variation tolerant true random number generator for 45 nm cmos high performance microprocessors
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Sanu Mathew, Himanshu Kaul, Amit Agarwal, Sudhir K Satpathy, Steven K Hsu, Suresh Srinivasan, Mark Anders, Farhana Sheikh, Ram KrishnamurthyAbstract:This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained programmable Clock Delay generators, along with an entropy-tracking feedback loop provide tolerance to 20% PVT variation-induced device mismatches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 μm2, while achieving: (i) 2.4 Gbps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V, 50°C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1's with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 14 Mbps, 5.6 μW, measured at 280 mV, 50°C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state operation, (vi) <;3% error while using an analytical ergodic Markov chain model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher energy-efficiency than previously reported implementations. Design modifications for robust operation in 22 nm high-volume manufacturing in the presence of 3σ process variations demonstrate scalability of the all-digital design to future technologies.
Sanu Mathew - One of the best experts on this subject based on the ideXlab platform.
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a 4 fj b Delay hardened physically unclonable function circuit with selective bit destabilization in 14 nm trigate cmos
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Sudhir K Satpathy, Sanu Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Vikram B Suresh, Steven K Hsu, Gregory K Chen, Ram KrishnamurthyAbstract:This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential Clock Delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid Clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.
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a 4fj bit Delay hardened physically unclonable function circuit with selective bit destabilization in 14nm tri gate cmos
Symposium on VLSI Circuits, 2016Co-Authors: Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Greg Chen, Ram Krishnamurthy, Vivek DeAbstract:A 1024-bit Delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential Clock Delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.
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2 4 gbps 7 mw all digital pvt variation tolerant true random number generator for 45 nm cmos high performance microprocessors
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Sanu Mathew, Himanshu Kaul, Amit Agarwal, Sudhir K Satpathy, Steven K Hsu, Suresh Srinivasan, Mark Anders, Farhana Sheikh, Ram KrishnamurthyAbstract:This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained programmable Clock Delay generators, along with an entropy-tracking feedback loop provide tolerance to 20% PVT variation-induced device mismatches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 μm2, while achieving: (i) 2.4 Gbps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V, 50°C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1's with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 14 Mbps, 5.6 μW, measured at 280 mV, 50°C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state operation, (vi) <;3% error while using an analytical ergodic Markov chain model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher energy-efficiency than previously reported implementations. Design modifications for robust operation in 22 nm high-volume manufacturing in the presence of 3σ process variations demonstrate scalability of the all-digital design to future technologies.
Himanshu Kaul - One of the best experts on this subject based on the ideXlab platform.
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a 4 fj b Delay hardened physically unclonable function circuit with selective bit destabilization in 14 nm trigate cmos
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Sudhir K Satpathy, Sanu Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Vikram B Suresh, Steven K Hsu, Gregory K Chen, Ram KrishnamurthyAbstract:This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential Clock Delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid Clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.
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a 4fj bit Delay hardened physically unclonable function circuit with selective bit destabilization in 14nm tri gate cmos
Symposium on VLSI Circuits, 2016Co-Authors: Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Greg Chen, Ram Krishnamurthy, Vivek DeAbstract:A 1024-bit Delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential Clock Delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.
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2 4 gbps 7 mw all digital pvt variation tolerant true random number generator for 45 nm cmos high performance microprocessors
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Sanu Mathew, Himanshu Kaul, Amit Agarwal, Sudhir K Satpathy, Steven K Hsu, Suresh Srinivasan, Mark Anders, Farhana Sheikh, Ram KrishnamurthyAbstract:This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained programmable Clock Delay generators, along with an entropy-tracking feedback loop provide tolerance to 20% PVT variation-induced device mismatches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 μm2, while achieving: (i) 2.4 Gbps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V, 50°C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1's with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 14 Mbps, 5.6 μW, measured at 280 mV, 50°C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state operation, (vi) <;3% error while using an analytical ergodic Markov chain model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher energy-efficiency than previously reported implementations. Design modifications for robust operation in 22 nm high-volume manufacturing in the presence of 3σ process variations demonstrate scalability of the all-digital design to future technologies.
Amit Agarwal - One of the best experts on this subject based on the ideXlab platform.
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a 4 fj b Delay hardened physically unclonable function circuit with selective bit destabilization in 14 nm trigate cmos
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Sudhir K Satpathy, Sanu Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Vikram B Suresh, Steven K Hsu, Gregory K Chen, Ram KrishnamurthyAbstract:This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential Clock Delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid Clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.
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a 4fj bit Delay hardened physically unclonable function circuit with selective bit destabilization in 14nm tri gate cmos
Symposium on VLSI Circuits, 2016Co-Authors: Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Greg Chen, Ram Krishnamurthy, Vivek DeAbstract:A 1024-bit Delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential Clock Delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.
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2 4 gbps 7 mw all digital pvt variation tolerant true random number generator for 45 nm cmos high performance microprocessors
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Sanu Mathew, Himanshu Kaul, Amit Agarwal, Sudhir K Satpathy, Steven K Hsu, Suresh Srinivasan, Mark Anders, Farhana Sheikh, Ram KrishnamurthyAbstract:This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out of metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained programmable Clock Delay generators, along with an entropy-tracking feedback loop provide tolerance to 20% PVT variation-induced device mismatches, enabling lowest-reported energy-consumption of 2.9 pJ/bit with a dense layout occupying 4004 μm2, while achieving: (i) 2.4 Gbps random bit throughput, 7 mW total power consumption with 0.7 mW leakage power component, measured at 1.1 V, 50°C, (ii) random bitstreams that passes all NIST RNG tests with raw entropy/bit measured up to 0.9999999993, (iii) good distribution of 1's with 4-bit entropy of 3.97996 and high-entropy pattern probability of 0.066 (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 14 Mbps, 5.6 μW, measured at 280 mV, 50°C, (v) 12 fine-grained high-entropy settings for the TRNG to dither in during steady-state operation, (vi) <;3% error while using an analytical ergodic Markov chain model for predicting pattern probabilities and (vii) 200x higher throughput and 9x higher energy-efficiency than previously reported implementations. Design modifications for robust operation in 22 nm high-volume manufacturing in the presence of 3σ process variations demonstrate scalability of the all-digital design to future technologies.
Vivek De - One of the best experts on this subject based on the ideXlab platform.
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a 4fj bit Delay hardened physically unclonable function circuit with selective bit destabilization in 14nm tri gate cmos
Symposium on VLSI Circuits, 2016Co-Authors: Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Greg Chen, Ram Krishnamurthy, Vivek DeAbstract:A 1024-bit Delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential Clock Delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.