The Experts below are selected from a list of 1107 Experts worldwide ranked by ideXlab platform

T. Ussmueller - One of the best experts on this subject based on the ideXlab platform.

  • A 20-Gbps low jitter analog Clock Recovery Circuit for ultra-wide band Radio systems
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: M. Hamouda, G. Fischer, R. Weigel, A. Baenisch, T. Ussmueller
    Abstract:

    This work describes the design of high speed Clock Recovery Circuit for UWB M-sequence based Radio systems in the analog domain to avoid the high power consumed in the analog to digital converters (ADC). The Clock Recovery Circuit depends on two modes, the coarse tuning mode and the fine tuning mode for final locking and tracking. It is illustrated, using this method, that low jitter is achieved while maintaining high acquisition range up to the tuning range of the VCO. The method depends on using a reference M-sequence in the receiver similar to the one used in the transmitter and an analog correlation Circuit. The Circuits are designed using a low cost 0.25μm 95GHz fmax SiGe-HBT-BiCMOS process technology consuming an estimated power of 185mW.

  • ISCAS - A 20-Gbps low jitter analog Clock Recovery Circuit for ultra-wide band Radio systems
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: M. Hamouda, G. Fischer, R. Weigel, A. Baenisch, T. Ussmueller
    Abstract:

    This work describes the design of high speed Clock Recovery Circuit for UWB M-sequence based Radio systems in the analog domain to avoid the high power consumed in the analog to digital converters (ADC). The Clock Recovery Circuit depends on two modes, the coarse tuning mode and the fine tuning mode for final locking and tracking. It is illustrated, using this method, that low jitter is achieved while maintaining high acquisition range up to the tuning range of the VCO. The method depends on using a reference M-sequence in the receiver similar to the one used in the transmitter and an analog correlation Circuit. The Circuits are designed using a low cost 0.25μm 95GHz f max SiGe-HBT-BiCMOS process technology consuming an estimated power of 185mW.

Behzad Razavi - One of the best experts on this subject based on the ideXlab platform.

  • a cmos Clock Recovery Circuit for 2 5 gb s nrz data
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: S.b. Anand, Behzad Razavi
    Abstract:

    This paper describes a phase-locked Clock Recovery Circuit that operates at 2.5 Gb/s in a 0.4-/spl mu/m digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered Clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core Circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8/spl times/0.4 mm/sup 2/.

  • a 2 5 gb s 15 mw Clock Recovery Circuit
    IEEE Journal of Solid-state Circuits, 1996
    Co-Authors: Behzad Razavi
    Abstract:

    This paper describes the design of a 2.5-Gb/s 15-mW Clock Recovery Circuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the Circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation. In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions. Fabricated in a 20-GHz 1-/spl mu/m BiCMOS technology, the Circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz.

  • A 30MHz Hybrid Analog/Digital Clock Recovery Circuit in 2m CMOS
    Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, 1
    Co-Authors: Behzad Razavi
    Abstract:

    A high-speed hybrid. Clock Recovery Circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 94% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 ppm/°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequeJlcy. The total power dissipation is about 600 mW and the active area is 30000 mill2; in a 2-µm single-poly double-metal n-well CMOS process.

  • A SelfCorrecting Clock Recovery Circuit
    Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, 1
    Co-Authors: Behzad Razavi
    Abstract:

    Conventional approaches to the problem of extracting Clock from NRZ data do not automatically hold the Clock in the center of the data eye. Other means must be used to keep the Clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The Circuit is both simple and self correcting.

M. Hamouda - One of the best experts on this subject based on the ideXlab platform.

  • A 20-Gbps low jitter analog Clock Recovery Circuit for ultra-wide band Radio systems
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: M. Hamouda, G. Fischer, R. Weigel, A. Baenisch, T. Ussmueller
    Abstract:

    This work describes the design of high speed Clock Recovery Circuit for UWB M-sequence based Radio systems in the analog domain to avoid the high power consumed in the analog to digital converters (ADC). The Clock Recovery Circuit depends on two modes, the coarse tuning mode and the fine tuning mode for final locking and tracking. It is illustrated, using this method, that low jitter is achieved while maintaining high acquisition range up to the tuning range of the VCO. The method depends on using a reference M-sequence in the receiver similar to the one used in the transmitter and an analog correlation Circuit. The Circuits are designed using a low cost 0.25μm 95GHz fmax SiGe-HBT-BiCMOS process technology consuming an estimated power of 185mW.

  • ISCAS - A 20-Gbps low jitter analog Clock Recovery Circuit for ultra-wide band Radio systems
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: M. Hamouda, G. Fischer, R. Weigel, A. Baenisch, T. Ussmueller
    Abstract:

    This work describes the design of high speed Clock Recovery Circuit for UWB M-sequence based Radio systems in the analog domain to avoid the high power consumed in the analog to digital converters (ADC). The Clock Recovery Circuit depends on two modes, the coarse tuning mode and the fine tuning mode for final locking and tracking. It is illustrated, using this method, that low jitter is achieved while maintaining high acquisition range up to the tuning range of the VCO. The method depends on using a reference M-sequence in the receiver similar to the one used in the transmitter and an analog correlation Circuit. The Circuits are designed using a low cost 0.25μm 95GHz f max SiGe-HBT-BiCMOS process technology consuming an estimated power of 185mW.

Jiawen Hu - One of the best experts on this subject based on the ideXlab platform.

  • A Clock Recovery Circuit for blind equalization multi-Gbps serial data links
    2006 IEEE International Symposium on Circuits and Systems, 2006
    Co-Authors: Jiawen Hu
    Abstract:

    This paper presents a Clock Recovery Circuit for multi-Gbps serial data link that extracts the timing information hidden in pulse amplitude modulation by exploiting its intrinsic cyclostationarity. In contrast to conventional Clock Recovery Circuit based on phase detector of Alexander or Hogge type, the proposed one is compatible with multi-level PAM data and linearly distorted data with closed eye diagram, and does not convert the inter-symbol interference into timing jitter. Hence it is well suited to be integrated as an a priori Clock generator in a blind equalizer of a multi-Gbps serial link receiver. The operation principles with related theoretical background as well as the Circuit implementation are discussed in detail

  • ISCAS - A Clock Recovery Circuit for blind equalization multi-Gbps serial data links
    2006 IEEE International Symposium on Circuits and Systems, 2006
    Co-Authors: Jiawen Hu
    Abstract:

    This paper presents a Clock Recovery Circuit for multi-Gbps serial data link that extracts the timing information hidden in pulse amplitude modulation by exploiting its intrinsic cyclostationarity. In contrast to conventional Clock Recovery Circuit based on phase detector of Alexander or Hogge type, the proposed one is compatible with multi-level PAM data and linearly distorted data with closed eye diagram, and does not convert the inter-symbol interference into timing jitter. Hence it is well suited to be integrated as an a priori Clock generator in a blind equalizer of a multi-Gbps serial link receiver. The operation principles with related theoretical background as well as the Circuit implementation are discussed in detail.

Woo-young Choi - One of the best experts on this subject based on the ideXlab platform.

  • A 5-Gb/s Half-Rate Clock Recovery Circuit
    2006
    Co-Authors: Woo-young Choi
    Abstract:

    A half-rate Clock Recovery Circuit for 5-Gb/s data rate was designed in 0.25-μm CMOS technology. The bang-bang phase detector was used for high-speed operation. The simulation results show that the half-rate Clock was successfully extracted from random bit data sequence up to 6-Gb/s. In initial measurement of the fabricated chip, 2.5-GHz Clock was extracted from 2.5Gb/s PRBS 2-1. Further measurement will be done and presented.

  • A 5-Gb/s Half-rate Clock Recovery Circuit in 0.25-μm CMOS Technology
    2006
    Co-Authors: Woo-young Choi
    Abstract:

    A half-rate Clock Recovery Circuit for 5-Gb/s data rate was designed in 0.25-μm CMOS technology. The bang-bang phase detector was used for high-speed operation. The simulation results show that the half-rate Clock was successfully extracted from random bit data sequence up to 6-Gb/s. In initial measurement of the fabricated chip, 2.5-GHz Clock was extracted from 2.5Gb/s PRBS 2-1. Further measurement will be done and presented.

  • 1.25/2.5-Gb/s burst-mode Clock Recovery Circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS
    2006 IEEE International Symposium on Circuits and Systems, 2006
    Co-Authors: Woo-young Choi
    Abstract:

    A burst-mode Clock Recovery Circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align Clock with data edges and can operate in half-rate Clocking mode, doubling data throughput, as well as in full-rate Clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0deg and 180deg according to the current Clock phase. A prototype chip was designed with 0.18-mum CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement

  • ISCAS - 1.25/2.5-Gb/s burst-mode Clock Recovery Circuit with a novel dual bit-rate structure in 0.18-/spl mu/m CMOS
    2006 IEEE International Symposium on Circuits and Systems, 2006
    Co-Authors: Woo-young Choi
    Abstract:

    A burst-mode Clock Recovery Circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align Clock with data edges and can operate in half-rate Clocking mode, doubling data throughput, as well as in full-rate Clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0/spl deg/ and 180/spl deg/ according to the current Clock phase. A prototype chip was designed with 0.18-/spl mu/m CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement.