The Experts below are selected from a list of 18201 Experts worldwide ranked by ideXlab platform
Alyssa B Apsel - One of the best experts on this subject based on the ideXlab platform.
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A low-power, process-and-temperature-compensated Ring Oscillator with addition-based current source
IEEE Transactions on Circuits and Systems I: Regular Papers, 2011Co-Authors: Xuan Zhang, Alyssa B ApselAbstract:The design of a 1.8 GHz 3-stage current-starved Ring Oscillator with a process- and temperature- compensated current source is presented. Without post-fabrication calibration or off-chip components, the proposed low variation circuit is able to achieve a 65.1% reduction in the normalized standard deviation of its center frequency at room temperature and 85 ppm/ $^{\circ}$ C temperature stability with no penalty in the oscillation frequency, the phase noise or the start-up time. Analysis on the impact of transistor scaling indicates that the same circuit topology can be applied to improve variability as feature size scales beyond the current deep submicron technology. Measurements taken on 167 test chips from two different lots fabricated in a standard 90 nm CMOS process show a 3x improvement in frequency variation compared to the baseline case of a conventional current-starved Ring Oscillator. The power and area for the proposed circuitry is 87 $\mu$W and 0.013 mm$^{2}$ compared to 54 $\mu$ W and 0.01 mm $^{2}$ in the baseline case.
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ISCAS - A process compensated 3-GHz Ring Oscillator
2009 IEEE International Symposium on Circuits and Systems, 2009Co-Authors: Xuan Zhang, Alyssa B ApselAbstract:In this paper, we present a high speed Ring Oscillator compensated for process, as well as temperature variation. No post-fabrication efforts or external clock reference is required to implement our process compensation scheme. By adding a novel control loop to the Ring Oscillator and leveraging a low process variation current source, we are able to reduce the typical variation from 10.2% to 2.7% for a 3-GHz three stage inverter chain Ring Oscillator. The compensation scheme developed in the paper is not limited to applications in Ring Oscillators, but can be used in all types of VCO designs.
Christian Plessl - One of the best experts on this subject based on the ideXlab platform.
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FPL - Exploration of Ring Oscillator design space for temperature measurements on FPGAs
22nd International Conference on Field Programmable Logic and Applications (FPL), 2012Co-Authors: Christoph Ruething, Andreas Agne, Markus Happe, Christian PlesslAbstract:While numerous publications have presented Ring Oscillator designs for temperature measurements a detailed study of the Ring Oscillator's design space is still missing. In this work, we introduce metrics for compaRing the performance and area efficiency of Ring Oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for Ring Oscillators for a Xilinx Virtex-5 platform FPGA.
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exploration of Ring Oscillator design space for temperature measurements on fpgas
Field-Programmable Logic and Applications, 2012Co-Authors: Christoph Ruething, Andreas Agne, Markus Happe, Christian PlesslAbstract:While numerous publications have presented Ring Oscillator designs for temperature measurements a detailed study of the Ring Oscillator's design space is still missing. In this work, we introduce metrics for compaRing the performance and area efficiency of Ring Oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for Ring Oscillators for a Xilinx Virtex-5 platform FPGA.
Xuan Zhang - One of the best experts on this subject based on the ideXlab platform.
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A low-power, process-and-temperature-compensated Ring Oscillator with addition-based current source
IEEE Transactions on Circuits and Systems I: Regular Papers, 2011Co-Authors: Xuan Zhang, Alyssa B ApselAbstract:The design of a 1.8 GHz 3-stage current-starved Ring Oscillator with a process- and temperature- compensated current source is presented. Without post-fabrication calibration or off-chip components, the proposed low variation circuit is able to achieve a 65.1% reduction in the normalized standard deviation of its center frequency at room temperature and 85 ppm/ $^{\circ}$ C temperature stability with no penalty in the oscillation frequency, the phase noise or the start-up time. Analysis on the impact of transistor scaling indicates that the same circuit topology can be applied to improve variability as feature size scales beyond the current deep submicron technology. Measurements taken on 167 test chips from two different lots fabricated in a standard 90 nm CMOS process show a 3x improvement in frequency variation compared to the baseline case of a conventional current-starved Ring Oscillator. The power and area for the proposed circuitry is 87 $\mu$W and 0.013 mm$^{2}$ compared to 54 $\mu$ W and 0.01 mm $^{2}$ in the baseline case.
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ISCAS - A process compensated 3-GHz Ring Oscillator
2009 IEEE International Symposium on Circuits and Systems, 2009Co-Authors: Xuan Zhang, Alyssa B ApselAbstract:In this paper, we present a high speed Ring Oscillator compensated for process, as well as temperature variation. No post-fabrication efforts or external clock reference is required to implement our process compensation scheme. By adding a novel control loop to the Ring Oscillator and leveraging a low process variation current source, we are able to reduce the typical variation from 10.2% to 2.7% for a 3-GHz three stage inverter chain Ring Oscillator. The compensation scheme developed in the paper is not limited to applications in Ring Oscillators, but can be used in all types of VCO designs.
Chien Yin - One of the best experts on this subject based on the ideXlab platform.
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temperature aware cooperative Ring Oscillator puf
Hardware-Oriented Security and Trust, 2009Co-Authors: Chien YinAbstract:Physical unclonable functions leverage the manufacture variations duRing silicon fabrication process and have found many security related applications. The Ring Oscillator PUF relies on pairs of Ring Oscillators which have sufficiently large difference in delay to generate reliable bits. Current RO PUF approaches use redundancy to provide reliability under different operating temperature and thus have very high hardware cost.We propose a temperature-aware cooperative (TAC) RO PUF implementation to reduce such cost. The basic idea is to allow a pair of Ring Oscillators to generate an unreliable bit as long as we can find means to convert it to a reliable bit. We define bit generation rules that explicitly take temperature into consideration and pair up the Ring Oscillator pairs so they can cooperate. Experiments on FPGA show that our approach can significantly improve the efficiency of the RO PUF implementation. With the same hardware that the current state-of-art approach requires to generate one reliable bit, our TAC RO PUF approach can generate as high as 1.8 reliable bits, that is, an 80% improvement in hardware utilization.
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HOST - Temperature-aware cooperative Ring Oscillator PUF
2009 IEEE International Workshop on Hardware-Oriented Security and Trust, 2009Co-Authors: Chien YinAbstract:Physical unclonable functions leverage the manufacture variations duRing silicon fabrication process and have found many security related applications. The Ring Oscillator PUF relies on pairs of Ring Oscillators which have sufficiently large difference in delay to generate reliable bits. Current RO PUF approaches use redundancy to provide reliability under different operating temperature and thus have very high hardware cost.We propose a temperature-aware cooperative (TAC) RO PUF implementation to reduce such cost. The basic idea is to allow a pair of Ring Oscillators to generate an unreliable bit as long as we can find means to convert it to a reliable bit. We define bit generation rules that explicitly take temperature into consideration and pair up the Ring Oscillator pairs so they can cooperate. Experiments on FPGA show that our approach can significantly improve the efficiency of the RO PUF implementation. With the same hardware that the current state-of-art approach requires to generate one reliable bit, our TAC RO PUF approach can generate as high as 1.8 reliable bits, that is, an 80% improvement in hardware utilization.
A.a. Abidi - One of the best experts on this subject based on the ideXlab platform.
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a 300 mhz cmos voltage controlled Ring Oscillator
IEEE Journal of Solid-state Circuits, 1990Co-Authors: S K Enam, A.a. AbidiAbstract:A voltage-controlled Ring Oscillator based on feedback derived from a weighted sum of two phases of an oscillation is described. A prototype fabricated in 1- mu m CMOS attains a maximum frequency of 320 MHz, with a controllable frequency range of 100 MHz. An almost sinusoidal waveform appears at the output across this range of frequencies. >
