The Experts below are selected from a list of 1914 Experts worldwide ranked by ideXlab platform
C R Bolognesi - One of the best experts on this subject based on the ideXlab platform.
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type ii inp gaassb double heteroJunction bipolar transistors with fmax 700 ghz
Applied Physics Express, 2014Co-Authors: Ralf Fluckiger, Rickard Lovblom, Maria Alexandrova, Olivier Ostinelli, C R BolognesiAbstract:The "type-II" staggered band lineup at the base-Collector Junction of InP/GaAsSb double-heteroJunction bipolar transistors (DHBTs) eliminates the current blocking effect observed in InP/GaInAs DHBTs and allows the use of a pure binary InP Collector that provides a high breakdown voltage and good thermal conductivity. Improvement of the power gain cutoff frequency fMAX requires a reduction in base resistance and/or base-Collector capacitance. We have decreased the base contact resistivity by in situ Ar sputtering immediately prior to the base contact deposition. The resulting DHBTs simultaneously feature fT = 429 GHz and fMAX = 715 GHz. To the best of the authors' knowledge, this is the highest reported fMAX for InP/GaAsSb-based DHBTs to date.
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ultrahigh performance staggered lineup type ii inp gaassb inp npn double heteroJunction bipolar transistors
Japanese Journal of Applied Physics, 2002Co-Authors: C R Bolognesi, M W Dvorak, N Matine, O J Pitts, S P WatkinsAbstract:We study the performance of staggered lineup NpN InP/GaAsSb/InP abrupt double heteroJunction bipolar transistors (DHBTs) intended for ultrahigh speed applications. With a peak fT of 305 GHz (and fMAX=300 GHz), InP/GaAsSb/InP DHBTs are currently the fastest bipolar transistors ever implemented, and as such may challenge sub-100 nm gate InP HEMTs for > 40 Gb/s applications: previously published criteria suggest current device performance should be suitable for 80–100 Gb/s OEICs. InP/GaAsSb/InP DHBTs feature high breakdown voltages and low offset and knee voltages, and extremely high current drive levels enabled by the lack of Collector current blocking at the staggered base/Collector Junction. InP/GaAsSb/InP DHBTs also feature important manufacturability advantages because the structure is entirely made up of uniform composition binary and ternary alloy layers.
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non blocking Collector inp gaas sub 0 51 sb sub 0 49 inp double heteroJunction bipolar transistors with a staggered lineup base Collector Junction
IEEE Electron Device Letters, 1999Co-Authors: C R Bolognesi, N Matine, R W Dvorak, S P WatkinsAbstract:We have developed lattice-matched InP/GaAs/sub 0.51/Sb/sub 0.49//InP NpN double heteroJunction bipolar transistors (DHBTs) which take advantage of the staggered ("type II") band lineup at InP/GaAs/sub 0.51/Sb/sub 0.49/ interfaces: in this system the GaAs/sub 0.51/Sb/sub 0.49/ base conduction band edge lies /spl sim/0.18 eV above the InP Collector conduction band, thus enabling the implementation of InP Collectors free of the current blocking effect encountered in conventional Ga/sub 0.47/In/sub 0.53/As base DHBTs. The structure results in very low Collector current offset voltages, low emitter-base turn-on voltages, and very nearly ideal base and Collector current characteristics with Junction ideality factors of n/sub B/=1.05 and n/sub c/=1.00. InP/GaAs/sub 0.51/Sb/sub 0.49//InP DHBTs appear well-suited to low-power applications, but can also be used in power applications by virtue of their InP Collector. The symmetry of the transistor band structure also lends itself to the potential integration of Collector-up and emitter-up devices.
G I Haddad - One of the best experts on this subject based on the ideXlab platform.
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high f sub max inp double heteroJunction bipolar transistors with chirped ingaas inp superlattice base Collector Junction grown by cbe
IEEE Electron Device Letters, 1997Co-Authors: Kyounghoon Yang, G O Munns, G I HaddadAbstract:We report the performance of InP Double HeteroJunction Bipolar Transistors (DHBT's) with a chirped InGaAs/InP superlattice B-C Junction grown by CBE. The B-C Junction of the DHBT was graded with a 10-period InGaAs/InP chirped superlattice (CSL) between the InGaAs base and the lightly doped InP Collector. A highly doped thin layer was also included at the end of the CSL to offset the quasi-electric field arising from the grade and suppress further the carrier blocking effect across the B-C heteroJunction. The InP/InGaAs CSL DHBT demonstrated a high BV/sub CEO/ of 18.3 V with a typical current gain of 55 with minimal carrier blocking up to high current densities. Maximum cutoff frequencies of f/sub max/=146 GHz and f/sub r/=71 GHz were obtained from the fabricated 2/spl times/10 /spl mu/m/sup 2/-emitter DHBT.
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double heteroJunction bipolar transistors with chirped ingaas inp superlattice base Collector Junction grown by cbe
International Conference on Indium Phosphide and Related Materials, 1997Co-Authors: Kyounghoon Yang, G O Munns, X Wang, G I HaddadAbstract:We report the performance of InP DHBTs with a chirped InGaAs/InP superlattice B-C Junction grown by CBE. The B-C Junction of the DHBT was graded with a 10-period InGaAs/InP chirped superlattice (CSL) between the InGaAs base and the lightly doped InP Collector. A highly doped thin layer was also included at the end of the CSL to offset the quasielectric field arising from the grade and suppress further the carrier blocking effect across the B-C heteroJunction. The InP/InGaAs CSL DHBT demonstrated a high BV/sub C/F/sub EO/ of 18 V with a typical current gain of 55 with minimal carrier blocking up to high current densities. Maximum cutoff frequencies of f/sub max/=146 GHz and f/sub /spl tau//=71 GHz were obtained from the fabricated 2/spl times/10 /spl mu/m/sup 2/-emitter DHBT.
Kyounghoon Yang - One of the best experts on this subject based on the ideXlab platform.
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high f sub max inp double heteroJunction bipolar transistors with chirped ingaas inp superlattice base Collector Junction grown by cbe
IEEE Electron Device Letters, 1997Co-Authors: Kyounghoon Yang, G O Munns, G I HaddadAbstract:We report the performance of InP Double HeteroJunction Bipolar Transistors (DHBT's) with a chirped InGaAs/InP superlattice B-C Junction grown by CBE. The B-C Junction of the DHBT was graded with a 10-period InGaAs/InP chirped superlattice (CSL) between the InGaAs base and the lightly doped InP Collector. A highly doped thin layer was also included at the end of the CSL to offset the quasi-electric field arising from the grade and suppress further the carrier blocking effect across the B-C heteroJunction. The InP/InGaAs CSL DHBT demonstrated a high BV/sub CEO/ of 18.3 V with a typical current gain of 55 with minimal carrier blocking up to high current densities. Maximum cutoff frequencies of f/sub max/=146 GHz and f/sub r/=71 GHz were obtained from the fabricated 2/spl times/10 /spl mu/m/sup 2/-emitter DHBT.
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double heteroJunction bipolar transistors with chirped ingaas inp superlattice base Collector Junction grown by cbe
International Conference on Indium Phosphide and Related Materials, 1997Co-Authors: Kyounghoon Yang, G O Munns, X Wang, G I HaddadAbstract:We report the performance of InP DHBTs with a chirped InGaAs/InP superlattice B-C Junction grown by CBE. The B-C Junction of the DHBT was graded with a 10-period InGaAs/InP chirped superlattice (CSL) between the InGaAs base and the lightly doped InP Collector. A highly doped thin layer was also included at the end of the CSL to offset the quasielectric field arising from the grade and suppress further the carrier blocking effect across the B-C heteroJunction. The InP/InGaAs CSL DHBT demonstrated a high BV/sub C/F/sub EO/ of 18 V with a typical current gain of 55 with minimal carrier blocking up to high current densities. Maximum cutoff frequencies of f/sub max/=146 GHz and f/sub /spl tau//=71 GHz were obtained from the fabricated 2/spl times/10 /spl mu/m/sup 2/-emitter DHBT.
K. Suzuki - One of the best experts on this subject based on the ideXlab platform.
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Optimum base-doping profile for minimum base transit time considering velocity saturation at base-Collector Junction and dependence of mobility and bandgap narrowing on doping concentration
IEEE Transactions on Electron Devices, 2001Co-Authors: K. SuzukiAbstract:We used variational calculus, the trial function, and the iterative procedure method to evaluate the optimum base doping concentration profile that will yield the minimum base transit time /spl tau//sub B/. All methods were extended to include the velocity saturation at the base Collector Junction, and the dependence of mobility and bandgap narrowing on the base doping concentration. We showed that all methods produce almost the same /spl tau//sub B/, although the profiles differ. Among them, the iterative method always produces the minimum /spl tau//sub B/ and variational calculus clearly shows the dependence of /spl tau//sub B/ on physical parameters.
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Base transit time of shallow-base bipolar transistors considering velocity saturation at base-Collector Junction
IEEE Transactions on Electron Devices, 1992Co-Authors: K. Suzuki, N. NakayamaAbstract:The authors studied the influence of the velocity saturation in the base-Collector depletion layer and compared the injected electron concentration profile, Collector current density, and base transit time with velocity saturation to those without. The Collector current with velocity saturation is only a little smaller than the current without saturation, but the injection electron concentration profile changes substantially when comparing currents with and without velocity saturation. The base transit time is increased by velocity saturation, and the ratio of base transit time with velocity saturation to that without velocity saturation increases as the base width decreases. Thus, velocity saturation must be considered in order to evaluate the base transit time of shallow-base bipolar transistors. The dependence of the base transit time on the doping profile was also analyzed, revealing that the base transit time of a box doping profile is increased more than that of a Gaussian doping profile.
S P Watkins - One of the best experts on this subject based on the ideXlab platform.
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ultrahigh performance staggered lineup type ii inp gaassb inp npn double heteroJunction bipolar transistors
Japanese Journal of Applied Physics, 2002Co-Authors: C R Bolognesi, M W Dvorak, N Matine, O J Pitts, S P WatkinsAbstract:We study the performance of staggered lineup NpN InP/GaAsSb/InP abrupt double heteroJunction bipolar transistors (DHBTs) intended for ultrahigh speed applications. With a peak fT of 305 GHz (and fMAX=300 GHz), InP/GaAsSb/InP DHBTs are currently the fastest bipolar transistors ever implemented, and as such may challenge sub-100 nm gate InP HEMTs for > 40 Gb/s applications: previously published criteria suggest current device performance should be suitable for 80–100 Gb/s OEICs. InP/GaAsSb/InP DHBTs feature high breakdown voltages and low offset and knee voltages, and extremely high current drive levels enabled by the lack of Collector current blocking at the staggered base/Collector Junction. InP/GaAsSb/InP DHBTs also feature important manufacturability advantages because the structure is entirely made up of uniform composition binary and ternary alloy layers.
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non blocking Collector inp gaas sub 0 51 sb sub 0 49 inp double heteroJunction bipolar transistors with a staggered lineup base Collector Junction
IEEE Electron Device Letters, 1999Co-Authors: C R Bolognesi, N Matine, R W Dvorak, S P WatkinsAbstract:We have developed lattice-matched InP/GaAs/sub 0.51/Sb/sub 0.49//InP NpN double heteroJunction bipolar transistors (DHBTs) which take advantage of the staggered ("type II") band lineup at InP/GaAs/sub 0.51/Sb/sub 0.49/ interfaces: in this system the GaAs/sub 0.51/Sb/sub 0.49/ base conduction band edge lies /spl sim/0.18 eV above the InP Collector conduction band, thus enabling the implementation of InP Collectors free of the current blocking effect encountered in conventional Ga/sub 0.47/In/sub 0.53/As base DHBTs. The structure results in very low Collector current offset voltages, low emitter-base turn-on voltages, and very nearly ideal base and Collector current characteristics with Junction ideality factors of n/sub B/=1.05 and n/sub c/=1.00. InP/GaAs/sub 0.51/Sb/sub 0.49//InP DHBTs appear well-suited to low-power applications, but can also be used in power applications by virtue of their InP Collector. The symmetry of the transistor band structure also lends itself to the potential integration of Collector-up and emitter-up devices.