The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform
A.p. Brunger - One of the best experts on this subject based on the ideXlab platform.
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Optimum flow rates in solar water heating systems with a counterflow exchanger
Solar Energy, 1992Co-Authors: K.g.t. Hollands, A.p. BrungerAbstract:Abstract Although optimum Collector flow rates in solar water heating systems have been broadly established, the existence of such an optimum has not been demonstrated for systems having a heat exchanger between the Collector fluid and the tank water to be heated. Starting from the premise that the overall exchanger conductance ( UA ) x can be conceptually held fixed while the flow rates are varied in search of an optimum, we show analytically that optimum flow rates do indeed exist on both Sides of the exchanger. We deduce that the optimum value R opt of the exchanger heat capacity ratio R —i.e., the optimum Collector-Side flow, relative to the tank-Side flow—is a function only of the conductance ratio ϱ = (UA) x F′U L A c , as follows: R opt = (1 + ϱ) ϱ . Moreover, an exchanger/Collector combination operating with R = R opt is shown to behave, for all practical purposes, like a direct water-heating Collector with its area reduced by the factor ϱ (1 + ϱ) . From this we deduce that there exists an optimum tank-Side flow rate m t, opt , in the same sense that there exists an optimum Collector flow rate m t, opt for systems without exchangers, and deduce the relation m t, opt = ( ϱ (1 + ϱ) ) q m opt , where q ≈ 0.4. Finally, we use this principle of equivalent behaviour to derive an expression for the most economical value of ( UA ) x .
K.g.t. Hollands - One of the best experts on this subject based on the ideXlab platform.
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Optimum flow rates in solar water heating systems with a counterflow exchanger
Solar Energy, 1992Co-Authors: K.g.t. Hollands, A.p. BrungerAbstract:Abstract Although optimum Collector flow rates in solar water heating systems have been broadly established, the existence of such an optimum has not been demonstrated for systems having a heat exchanger between the Collector fluid and the tank water to be heated. Starting from the premise that the overall exchanger conductance ( UA ) x can be conceptually held fixed while the flow rates are varied in search of an optimum, we show analytically that optimum flow rates do indeed exist on both Sides of the exchanger. We deduce that the optimum value R opt of the exchanger heat capacity ratio R —i.e., the optimum Collector-Side flow, relative to the tank-Side flow—is a function only of the conductance ratio ϱ = (UA) x F′U L A c , as follows: R opt = (1 + ϱ) ϱ . Moreover, an exchanger/Collector combination operating with R = R opt is shown to behave, for all practical purposes, like a direct water-heating Collector with its area reduced by the factor ϱ (1 + ϱ) . From this we deduce that there exists an optimum tank-Side flow rate m t, opt , in the same sense that there exists an optimum Collector flow rate m t, opt for systems without exchangers, and deduce the relation m t, opt = ( ϱ (1 + ϱ) ) q m opt , where q ≈ 0.4. Finally, we use this principle of equivalent behaviour to derive an expression for the most economical value of ( UA ) x .
P. Adeva - One of the best experts on this subject based on the ideXlab platform.
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Development and Evolution of Texture in Mg–Zr Alloy Deposited by Physical Vapor Deposition
Journal of Materials Research, 2002Co-Authors: G. Garcés, P. AdevaAbstract:The development and evolution of texture in a Mg–10.6%wt Zr deposit obtained by physical vapor deposition was studied. The deposit exhibits a microstructure characterized by elongated grains with the [0001] direction parallel to the deposit growth direction. The volume fraction of the basal plane component increases throughout the thickness from 45% at the Collector Side up to around 70%. The minimization of interfacial energy of (0001) planes induces the initial texture at the earliest stage of the deposit formation. Furthermore, the increase in the volume fraction of the (0001) component during deposit growth is provoked by texture competition, which results in the development of grains with the [0001] direction parallel to the deposit growth direction.
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texture of magnesium alloy films growth by physical vapour deposition pvd
Journal of Alloys and Compounds, 2000Co-Authors: G. Garcés, M C Cristina, Marcelino Torralba, P. AdevaAbstract:Abstract The texture developed by four physical vapor deposited Mg alloys grown at two Collector temperatures and their correlation with the microstructure have been studied. The alloys Mg–2.3Zr, Mg–10.6Zr and Mg–12Ti (wt%) deposited at around 150°C exhibited elongated grains growing in the normal direction to the deposit surface, but tilted with respect to the Z axis, with pores and cracks at the boundaries. A strong fibre texture of the ( 0001 ) basal plane component forming the fibre axis and the normal to the substrate plane an angle of 24, 18 or 12° depending on alloying element concentration has been found. The Mg–14Ti–1Al–0.9Mn (wt%) alloy, deposited at higher temperature, consisted of a region of columnar grains growing from the Collector Side followed by a thin region of equiaxed grains. Furthermore, a fibre texture with two components, the ( 0002 ) basal plane and the ( 1120 ) and the ( 1010 ) components in the Collector and free surfaces, respectively, were present. Differences found in this alloy with respect to the alloys deposited at lower temperature were related to the surface diffusion phenomenon of adatoms caused by a higher Collector temperature. The change in the second texture component from the Collector to the free surface can explained by the decrease in the deposit strain energy.
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Texture of magnesium alloy films growth by physical vapour deposition (PVD)
Journal of Alloys and Compounds, 2000Co-Authors: G. Garcés, M C Cristina, Marcelino Torralba, P. AdevaAbstract:The texture developed by four physical vapor deposited Mg alloys grown at two Collector temperatures and their correlation with the microstructure have been studied. The alloys Mg-2.3Zr, Mg-10.6Zr and Mg-12Ti (wt%) deposited at around 150°C exhibited elongated grains growing in the normal direction to the deposit surface, but tilted with respect to the Z axis, with pores and cracks at the boundaries. A strong fibre texture of the (0001) basal plane component forming the fibre axis and the normal to the substrate plane an angle of 24, 18 or 12° depending on alloying element concentration has been found. The Mg-14Ti-1Al-0.9Mn (wt%) alloy, deposited at higher temperature, consisted of a region of columnar grains growing from the Collector Side followed by a thin region of equiaxed grains. Furthermore, a fibre texture with two components, the (0002) basal plane and the (112̄0) and the (101̄0) components in the Collector and free surfaces, respectively, were present. Differences found in this alloy with respect to the alloys deposited at lower temperature were related to the surface diffusion phenomenon of adatoms caused by a higher Collector temperature. The change in the second texture component from the Collector to the free surface can explained by the decrease in the deposit strain energy.Peer Reviewe
Longxing Shi - One of the best experts on this subject based on the ideXlab platform.
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Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy
IEEE Transactions on Electron Devices, 2019Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Shilin Cao, Jianfeng Zhao, Longxing ShiAbstract:In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, Collector–emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the Collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ can be realized by lowering the transition voltage from SRP to RRP ( ${V} _{\text {A}}$ ). Low electric potential from the emitter Side can be delivered to the Collector Side through the undepleted regions in P-pillar, which largely determine ${V} _{\text {A}}$ . According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an ${E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3$ % lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V.
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500-V Silicon-On-Insulator Lateral IGBT With W-Shaped n-Typed Buffer and Composite p-Typed Collectors
IEEE Transactions on Electron Devices, 2019Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Shilin Cao, Yanqin Zou, Jianfeng Zhao, Longxing ShiAbstract:A novel 500-V rated silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT), featuring a W-shaped n-typed buffer and p-typed composite Collectors, is proposed for the first time in this paper. The composite Collectors which consist of a high-doped p+ layer and a low-doped p− layer can maintain a high level of Collector-Side hole injection in ON-state; the low-doped p− layer combining with the W-shaped buffer provides a low barrier path for electron extraction during turn-off; thus, high current capability and high turn-off speed can be realized at the same time. The measurement results show that 67.3% decrease in turn-off time can be obtained at the expense of only 6.3% of current capability. Compared with the standard SOI-LIGBT, no additional processing steps or process modifications are required for the proposed SOI-LIGBT. The low-doped p− Collector is formed simultaneously with the emitter-Side p-well while the W-shaped buffer is formed by diffusion overlapping of two neighboring windows. At 125 °C, the proposed SOI-LIGBT exhibits an ON-state voltage drop of 2.48 V, a saturated current density of 420 A/cm2, a turn-off time of $>4~\mu \text{s}$ , allowing significant improvements in power loss, operating frequency, and ruggedness for single-chip intelligent power ICs.
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Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches
IEEE Transactions on Electron Devices, 2017Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Longxing Shi, Jian Chen, Desheng DingAbstract:A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter Side ( ${T}_{\textit {E}})$ and near the Collector Side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter Side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the Collector Side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.
Long Zhang - One of the best experts on this subject based on the ideXlab platform.
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Analysis of OFF-state dynamic avalanche instability in silicon-on-insulator lateral IGBTs at low temperature
Microelectronics Reliability, 2020Co-Authors: Long Zhang, Jing Zhu, Shilin Cao, Gong Jinli, Zexin Zhu, Cao Mengling, Weifeng SunAbstract:Abstract The dynamic avalanche instability in the silicon-on-insulator (SOI) lateral insulated-gate bipolar transistors (LIGBT) at low temperature is investigated. The measured results show a time-dependent Collector-emitter voltage (VCE) walk event at –40 °C under the OFF-state dynamic avalanche conditions. A charge couple is proposed and TCAD simulations are performed for the mechanism revealing. It is found that the dynamic avalanche instability is closely related to the hole accumulation at the Collector-Side bottom, the depletion in P-type substrate (P-sub) and the transfer of the breakdown spot. The optimization strategy for the dynamic avalanche stability is drawn based on the revealed mechanism. The VCE walk can be suppressed or eliminated by preventing the dynamic expansion/shrinking behaviour of the depletion layer in substrate or satisfying an equal relationship between the vertical breakdown voltage (BVV) and the lateral breakdown voltage (BVL). With different device types, Collector structures, N-drift lengths, BOX thicknesses, substrate biases and substrate types, the VCE walk events at low temperature (–40 °C) are comprehensively discussed in this paper. The VCE walk can be completely eliminated through replacing the P-sub by the N-type substrate (N-sub).
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500-V Silicon-On-Insulator Lateral IGBT With W-Shaped n-Typed Buffer and Composite p-Typed Collectors
IEEE Transactions on Electron Devices, 2019Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Shilin Cao, Yanqin Zou, Jianfeng Zhao, Longxing ShiAbstract:A novel 500-V rated silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT), featuring a W-shaped n-typed buffer and p-typed composite Collectors, is proposed for the first time in this paper. The composite Collectors which consist of a high-doped p+ layer and a low-doped p− layer can maintain a high level of Collector-Side hole injection in ON-state; the low-doped p− layer combining with the W-shaped buffer provides a low barrier path for electron extraction during turn-off; thus, high current capability and high turn-off speed can be realized at the same time. The measurement results show that 67.3% decrease in turn-off time can be obtained at the expense of only 6.3% of current capability. Compared with the standard SOI-LIGBT, no additional processing steps or process modifications are required for the proposed SOI-LIGBT. The low-doped p− Collector is formed simultaneously with the emitter-Side p-well while the W-shaped buffer is formed by diffusion overlapping of two neighboring windows. At 125 °C, the proposed SOI-LIGBT exhibits an ON-state voltage drop of 2.48 V, a saturated current density of 420 A/cm2, a turn-off time of $>4~\mu \text{s}$ , allowing significant improvements in power loss, operating frequency, and ruggedness for single-chip intelligent power ICs.
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Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy
IEEE Transactions on Electron Devices, 2019Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Shilin Cao, Jianfeng Zhao, Longxing ShiAbstract:In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, Collector–emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the Collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ can be realized by lowering the transition voltage from SRP to RRP ( ${V} _{\text {A}}$ ). Low electric potential from the emitter Side can be delivered to the Collector Side through the undepleted regions in P-pillar, which largely determine ${V} _{\text {A}}$ . According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an ${E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3$ % lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V.
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Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches
IEEE Transactions on Electron Devices, 2017Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Longxing Shi, Jian Chen, Desheng DingAbstract:A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter Side ( ${T}_{\textit {E}})$ and near the Collector Side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter Side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the Collector Side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.
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500 V dual gate deep-oxide trench SOI-LIGBT with improved short-circuit immunity
Electronics Letters, 2015Co-Authors: Long Zhang, Jing Zhu, Weifeng SunAbstract:A 500 V deep-oxide trench silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with improved short-circuit capability is proposed. The structure features dual trench gates: one gate (G1) extended to the buried oxide and the other gate (G2) arranged in the deep-oxide trench in the drift region. In the off-state, G2 acts as an emitter-Side field plate to shield the lateral electric field from the Collector Side. In the on-state, negative voltage is applied to G2, leading to a hole inversion layer close to the deep-oxide trench. The hole inversion layer reroutes the hole current and provides an additional heat dissipation path. Experimental results show that the proposed structure exhibits high short-circuit immunity without degradation of the breakdown voltage. The short-circuit withstand time of the proposed structure is 1.55 times that of the conventional one, when the voltage of G2 is −5 V.